[2/2] drm/i915: Adjust sideband locking a bit for CHV/VLV
diff mbox

Message ID 1432662151-11760-2-git-send-email-ville.syrjala@linux.intel.com
State New
Headers show

Commit Message

Ville Syrjälä May 26, 2015, 5:42 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

chv_enable_pll() doesn't need to hold sb_lock for the entire duration of
the function. Drop the lock as soon as possible.

valleyview_set_cdclk() does a potential lock+unlock+lock+unlock cycle
with sb_lock. Move Grab the lock a few lines earlier so we can make do
with a single lock+unlock cycle always.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

Jani Nikula May 27, 2015, 8:03 a.m. UTC | #1
On Tue, 26 May 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> chv_enable_pll() doesn't need to hold sb_lock for the entire duration of
> the function. Drop the lock as soon as possible.
>
> valleyview_set_cdclk() does a potential lock+unlock+lock+unlock cycle
> with sb_lock. Move Grab the lock a few lines earlier so we can make do

Move Grab?

Anyway, both patches are

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> with a single lock+unlock cycle always.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 72b6529..067b1de 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1668,6 +1668,8 @@ static void chv_enable_pll(struct intel_crtc *crtc,
>  	tmp |= DPIO_DCLKP_EN;
>  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
>  
> +	mutex_unlock(&dev_priv->sb_lock);
> +
>  	/*
>  	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
>  	 */
> @@ -1683,8 +1685,6 @@ static void chv_enable_pll(struct intel_crtc *crtc,
>  	/* not sure when this should be written */
>  	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
>  	POSTING_READ(DPLL_MD(pipe));
> -
> -	mutex_unlock(&dev_priv->sb_lock);
>  }
>  
>  static int intel_num_dvo_pipes(struct drm_device *dev)
> @@ -5780,12 +5780,13 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
>  	}
>  	mutex_unlock(&dev_priv->rps.hw_lock);
>  
> +	mutex_lock(&dev_priv->sb_lock);
> +
>  	if (cdclk == 400000) {
>  		u32 divider;
>  
>  		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
>  
> -		mutex_lock(&dev_priv->sb_lock);
>  		/* adjust cdclk divider */
>  		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
>  		val &= ~DISPLAY_FREQUENCY_VALUES;
> @@ -5796,10 +5797,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
>  			      DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
>  			     50))
>  			DRM_ERROR("timed out waiting for CDclk change\n");
> -		mutex_unlock(&dev_priv->sb_lock);
>  	}
>  
> -	mutex_lock(&dev_priv->sb_lock);
>  	/* adjust self-refresh exit latency value */
>  	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
>  	val &= ~0x7f;
> @@ -5813,6 +5812,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
>  	else
>  		val |= 3000 / 250; /* 3.0 usec */
>  	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
> +
>  	mutex_unlock(&dev_priv->sb_lock);
>  
>  	vlv_update_cdclk(dev);
> -- 
> 2.3.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Ville Syrjälä May 27, 2015, 8:05 a.m. UTC | #2
On Wed, May 27, 2015 at 11:03:09AM +0300, Jani Nikula wrote:
> On Tue, 26 May 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > chv_enable_pll() doesn't need to hold sb_lock for the entire duration of
> > the function. Drop the lock as soon as possible.
> >
> > valleyview_set_cdclk() does a potential lock+unlock+lock+unlock cycle
> > with sb_lock. Move Grab the lock a few lines earlier so we can make do
> 
> Move Grab?

s/Move //

> 
> Anyway, both patches are
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> > with a single lock+unlock cycle always.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 72b6529..067b1de 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1668,6 +1668,8 @@ static void chv_enable_pll(struct intel_crtc *crtc,
> >  	tmp |= DPIO_DCLKP_EN;
> >  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
> >  
> > +	mutex_unlock(&dev_priv->sb_lock);
> > +
> >  	/*
> >  	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
> >  	 */
> > @@ -1683,8 +1685,6 @@ static void chv_enable_pll(struct intel_crtc *crtc,
> >  	/* not sure when this should be written */
> >  	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> >  	POSTING_READ(DPLL_MD(pipe));
> > -
> > -	mutex_unlock(&dev_priv->sb_lock);
> >  }
> >  
> >  static int intel_num_dvo_pipes(struct drm_device *dev)
> > @@ -5780,12 +5780,13 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> >  	}
> >  	mutex_unlock(&dev_priv->rps.hw_lock);
> >  
> > +	mutex_lock(&dev_priv->sb_lock);
> > +
> >  	if (cdclk == 400000) {
> >  		u32 divider;
> >  
> >  		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
> >  
> > -		mutex_lock(&dev_priv->sb_lock);
> >  		/* adjust cdclk divider */
> >  		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
> >  		val &= ~DISPLAY_FREQUENCY_VALUES;
> > @@ -5796,10 +5797,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> >  			      DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
> >  			     50))
> >  			DRM_ERROR("timed out waiting for CDclk change\n");
> > -		mutex_unlock(&dev_priv->sb_lock);
> >  	}
> >  
> > -	mutex_lock(&dev_priv->sb_lock);
> >  	/* adjust self-refresh exit latency value */
> >  	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
> >  	val &= ~0x7f;
> > @@ -5813,6 +5812,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> >  	else
> >  		val |= 3000 / 250; /* 3.0 usec */
> >  	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
> > +
> >  	mutex_unlock(&dev_priv->sb_lock);
> >  
> >  	vlv_update_cdclk(dev);
> > -- 
> > 2.3.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
Daniel Vetter May 27, 2015, 12:11 p.m. UTC | #3
On Wed, May 27, 2015 at 11:03:09AM +0300, Jani Nikula wrote:
> On Tue, 26 May 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > chv_enable_pll() doesn't need to hold sb_lock for the entire duration of
> > the function. Drop the lock as soon as possible.
> >
> > valleyview_set_cdclk() does a potential lock+unlock+lock+unlock cycle
> > with sb_lock. Move Grab the lock a few lines earlier so we can make do
> 
> Move Grab?

Fixed and both patches applied, thanks.
-Daniel

> 
> Anyway, both patches are
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> > with a single lock+unlock cycle always.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 72b6529..067b1de 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1668,6 +1668,8 @@ static void chv_enable_pll(struct intel_crtc *crtc,
> >  	tmp |= DPIO_DCLKP_EN;
> >  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
> >  
> > +	mutex_unlock(&dev_priv->sb_lock);
> > +
> >  	/*
> >  	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
> >  	 */
> > @@ -1683,8 +1685,6 @@ static void chv_enable_pll(struct intel_crtc *crtc,
> >  	/* not sure when this should be written */
> >  	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> >  	POSTING_READ(DPLL_MD(pipe));
> > -
> > -	mutex_unlock(&dev_priv->sb_lock);
> >  }
> >  
> >  static int intel_num_dvo_pipes(struct drm_device *dev)
> > @@ -5780,12 +5780,13 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> >  	}
> >  	mutex_unlock(&dev_priv->rps.hw_lock);
> >  
> > +	mutex_lock(&dev_priv->sb_lock);
> > +
> >  	if (cdclk == 400000) {
> >  		u32 divider;
> >  
> >  		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
> >  
> > -		mutex_lock(&dev_priv->sb_lock);
> >  		/* adjust cdclk divider */
> >  		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
> >  		val &= ~DISPLAY_FREQUENCY_VALUES;
> > @@ -5796,10 +5797,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> >  			      DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
> >  			     50))
> >  			DRM_ERROR("timed out waiting for CDclk change\n");
> > -		mutex_unlock(&dev_priv->sb_lock);
> >  	}
> >  
> > -	mutex_lock(&dev_priv->sb_lock);
> >  	/* adjust self-refresh exit latency value */
> >  	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
> >  	val &= ~0x7f;
> > @@ -5813,6 +5812,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> >  	else
> >  		val |= 3000 / 250; /* 3.0 usec */
> >  	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
> > +
> >  	mutex_unlock(&dev_priv->sb_lock);
> >  
> >  	vlv_update_cdclk(dev);
> > -- 
> > 2.3.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 72b6529..067b1de 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1668,6 +1668,8 @@  static void chv_enable_pll(struct intel_crtc *crtc,
 	tmp |= DPIO_DCLKP_EN;
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
 
+	mutex_unlock(&dev_priv->sb_lock);
+
 	/*
 	 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
 	 */
@@ -1683,8 +1685,6 @@  static void chv_enable_pll(struct intel_crtc *crtc,
 	/* not sure when this should be written */
 	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
 	POSTING_READ(DPLL_MD(pipe));
-
-	mutex_unlock(&dev_priv->sb_lock);
 }
 
 static int intel_num_dvo_pipes(struct drm_device *dev)
@@ -5780,12 +5780,13 @@  static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
 	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
+	mutex_lock(&dev_priv->sb_lock);
+
 	if (cdclk == 400000) {
 		u32 divider;
 
 		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 
-		mutex_lock(&dev_priv->sb_lock);
 		/* adjust cdclk divider */
 		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 		val &= ~DISPLAY_FREQUENCY_VALUES;
@@ -5796,10 +5797,8 @@  static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
 			      DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
 			     50))
 			DRM_ERROR("timed out waiting for CDclk change\n");
-		mutex_unlock(&dev_priv->sb_lock);
 	}
 
-	mutex_lock(&dev_priv->sb_lock);
 	/* adjust self-refresh exit latency value */
 	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 	val &= ~0x7f;
@@ -5813,6 +5812,7 @@  static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
 	else
 		val |= 3000 / 250; /* 3.0 usec */
 	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
+
 	mutex_unlock(&dev_priv->sb_lock);
 
 	vlv_update_cdclk(dev);