[RFC] Fix omap3 booting with thumb2 compiled kernel
diff mbox

Message ID 20150527215545.GA30984@atomide.com
State New
Headers show

Commit Message

Tony Lindgren May 27, 2015, 9:55 p.m. UTC
The power management related assembly needs to interact with
ARM mode bootrom code, so we need to keep most of the related
assembly in ARM mode.

Currently we are entering into and ARM mode assembly function
from thumb2 mode, so we need to make sure we switch to ARM
mode. And we need to do that again after the cache flush.

---

Kevin told me about this earlier today.. Anybody got better ideas
for a fix here?

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Comments

Kevin Hilman May 27, 2015, 10:19 p.m. UTC | #1
[ fix email for Dave Martin, +Tyler ]

Tony Lindgren <tony@atomide.com> writes:

> The power management related assembly needs to interact with
> ARM mode bootrom code, so we need to keep most of the related
> assembly in ARM mode.
>
> Currently we are entering into and ARM mode assembly function
> from thumb2 mode, so we need to make sure we switch to ARM
> mode. And we need to do that again after the cache flush.
>
> ---
>
> Kevin told me about this earlier today.. 


And for full boot log/panics, see the kernelci.org thumb2 kernel boots
that fail: http://kernelci.org/boot/?THUMB2_KERNEL&fail

> Anybody got better ideas for a fix here?

FWIW, a quick test of this patch makes my omap3-beagle-xm pass a simple
boot test, but it fails with off idle.

Kevin
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Patch
diff mbox

--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -151,6 +151,17 @@  ENTRY(save_secure_ram_context_sz)
  */
 	.align	3
 ENTRY(omap34xx_cpu_suspend)
+
+	/*
+	 * This ARM assembly can also be called from thumb2 kernel code.
+	 * Make sure we switch to ARM mode first.
+	 */
+ THUMB(	.thumb		)
+ THUMB(	.align		)
+ THUMB(	bx	pc	)
+ THUMB(	nop		)
+	.arm
+
 	stmfd	sp!, {r4 - r11, lr}	@ save registers on stack
 
 	/*
@@ -187,6 +198,18 @@  save_context_wfi:
 	bx	r1
 
 	/*
+	 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
+	 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
+	 * This sequence switches back to ARM.  Note that .align may insert a
+	 * nop: bx pc needs to be word-aligned in order to work.
+	 */
+ THUMB(	.thumb		)
+ THUMB(	.align		)
+ THUMB(	bx	pc	)
+ THUMB(	nop		)
+	.arm
+
+	/*
 	 * Clear the SCTLR.C bit to prevent further data cache
 	 * allocation. Clearing SCTLR.C would make all the data accesses
 	 * strongly ordered and would not hit the cache.
@@ -203,12 +226,8 @@  save_context_wfi:
 	 */
 	ldr	r1, kernel_flush
 	blx	r1
-	/*
-	 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
-	 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
-	 * This sequence switches back to ARM.  Note that .align may insert a
-	 * nop: bx pc needs to be word-aligned in order to work.
-	 */
+
+	/* See the comments above about v7_flush_dcache_all */
  THUMB(	.thumb		)
  THUMB(	.align		)
  THUMB(	bx	pc	)