From patchwork Wed May 27 21:55:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 6494551 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8D752C0020 for ; Wed, 27 May 2015 21:55:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 93D51206BA for ; Wed, 27 May 2015 21:55:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AF31A206E9 for ; Wed, 27 May 2015 21:55:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752437AbbE0Vzt (ORCPT ); Wed, 27 May 2015 17:55:49 -0400 Received: from muru.com ([72.249.23.125]:54193 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751968AbbE0Vzs (ORCPT ); Wed, 27 May 2015 17:55:48 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id DAF9E819D; Wed, 27 May 2015 21:57:20 +0000 (UTC) Date: Wed, 27 May 2015 14:55:46 -0700 From: Tony Lindgren To: linux-omap@vger.kernel.org Cc: Kevin Hilman , Arnd Bergmann , Dave Martin , linux-arm-kernel@lists.infradead.org Subject: [RFC] Fix omap3 booting with thumb2 compiled kernel Message-ID: <20150527215545.GA30984@atomide.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The power management related assembly needs to interact with ARM mode bootrom code, so we need to keep most of the related assembly in ARM mode. Currently we are entering into and ARM mode assembly function from thumb2 mode, so we need to make sure we switch to ARM mode. And we need to do that again after the cache flush. --- Kevin told me about this earlier today.. Anybody got better ideas for a fix here? -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -151,6 +151,17 @@ ENTRY(save_secure_ram_context_sz) */ .align 3 ENTRY(omap34xx_cpu_suspend) + + /* + * This ARM assembly can also be called from thumb2 kernel code. + * Make sure we switch to ARM mode first. + */ + THUMB( .thumb ) + THUMB( .align ) + THUMB( bx pc ) + THUMB( nop ) + .arm + stmfd sp!, {r4 - r11, lr} @ save registers on stack /* @@ -187,6 +198,18 @@ save_context_wfi: bx r1 /* + * The kernel doesn't interwork: v7_flush_dcache_all in particluar will + * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. + * This sequence switches back to ARM. Note that .align may insert a + * nop: bx pc needs to be word-aligned in order to work. + */ + THUMB( .thumb ) + THUMB( .align ) + THUMB( bx pc ) + THUMB( nop ) + .arm + + /* * Clear the SCTLR.C bit to prevent further data cache * allocation. Clearing SCTLR.C would make all the data accesses * strongly ordered and would not hit the cache. @@ -203,12 +226,8 @@ save_context_wfi: */ ldr r1, kernel_flush blx r1 - /* - * The kernel doesn't interwork: v7_flush_dcache_all in particluar will - * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. - * This sequence switches back to ARM. Note that .align may insert a - * nop: bx pc needs to be word-aligned in order to work. - */ + + /* See the comments above about v7_flush_dcache_all */ THUMB( .thumb ) THUMB( .align ) THUMB( bx pc )