From patchwork Sun May 31 04:27:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhichao Huang X-Patchwork-Id: 6515121 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2A3F19F1C1 for ; Sun, 31 May 2015 04:29:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4FA0D20637 for ; Sun, 31 May 2015 04:29:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 574282062F for ; Sun, 31 May 2015 04:29:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757878AbbEaE3B (ORCPT ); Sun, 31 May 2015 00:29:01 -0400 Received: from mail-pa0-f53.google.com ([209.85.220.53]:36648 "EHLO mail-pa0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754741AbbEaE3A (ORCPT ); Sun, 31 May 2015 00:29:00 -0400 Received: by pacux9 with SMTP id ux9so45656813pac.3 for ; Sat, 30 May 2015 21:28:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SB/XcO485d9PKbtq1tLUWzR5zsw4eYyA1xA/mgRiebE=; b=ToO455pw4pISuaATL+WEAYjPiBlLN0qgMi9HvTpeHilu3abgQ22g7I6D6PoxHL20hH cR0OuoevdgpSQhEn4IqGH1CIxlhba0yoLAv/oqNPsJoC+8GeTaWVBK+6LxWi71v7LB6A 9MKFlBAJlXtubvCe+ARKj5MA9Pej1bMnJ9XIaVRCoLZWOtM1vBeYXv32iLanB36djcJR tIDiwHc0WGrJloH0KZgMlVl6JmrhyuP82NZ0qcJjsoUpusg9DKbvRo+nXukNdBRPuYV5 Se4jFLtMLIWeUv3XA5Yaw5th79JuMMoAOMaNSbdDsjxSV+zjfdTfVi7PC/HY8N4HxO2F untQ== X-Gm-Message-State: ALoCoQlJoRgziGoyiLIHBwSJofVJiccnwziPNjKWcsqGGhmmcUuNMS1geOGgwVF53ErwLUbHY5Qn X-Received: by 10.70.0.67 with SMTP id 3mr28670952pdc.152.1433046539555; Sat, 30 May 2015 21:28:59 -0700 (PDT) Received: from localhost ([167.160.116.87]) by mx.google.com with ESMTPSA id t2sm578270pdo.81.2015.05.30.21.28.56 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sat, 30 May 2015 21:28:58 -0700 (PDT) From: Zhichao Huang To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, alex.bennee@linaro.org, will.deacon@arm.com Cc: huangzhichao@huawei.com, Zhichao Huang Subject: [PATCH v2 07/11] KVM: arm: add trap handlers for 64-bit debug registers Date: Sun, 31 May 2015 12:27:08 +0800 Message-Id: <1433046432-1824-8-git-send-email-zhichao.huang@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1433046432-1824-1-git-send-email-zhichao.huang@linaro.org> References: <1433046432-1824-1-git-send-email-zhichao.huang@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add handlers for all the 64-bit debug registers. There is an overlap between 32 and 64bit registers. Make sure that 64-bit registers preceding 32-bit ones. Signed-off-by: Zhichao Huang --- arch/arm/kvm/coproc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index 59b65b7..eeee648 100644 --- a/arch/arm/kvm/coproc.c +++ b/arch/arm/kvm/coproc.c @@ -435,9 +435,17 @@ static const struct coproc_reg cp15_regs[] = { { CRn( 1), CRm((n)), Op1( 0), Op2( 1), is32, trap_raz_wi } /* + * Architected CP14 registers. + * * Trapped cp14 registers. We generally ignore most of the external * debug, on the principle that they don't really make sense to a * guest. Revisit this one day, whould this principle change. + * + * CRn denotes the primary register number, but is copied to the CRm in the + * user space API for 64-bit register access in line with the terminology used + * in the ARM ARM. + * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit + * registers preceding 32-bit ones. */ static const struct coproc_reg cp14_regs[] = { /* DBGIDR */ @@ -445,10 +453,14 @@ static const struct coproc_reg cp14_regs[] = { /* DBGDTRRXext */ { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, trap_raz_wi }, DBG_BCR_BVR_WCR_WVR(0), + /* DBGDRAR (64bit) */ + { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is64, trap_raz_wi}, /* DBGDSCRint */ { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, trap_dbgdscr, NULL, cp14_DBGDSCRext }, DBG_BCR_BVR_WCR_WVR(1), + /* DBGDSAR (64bit) */ + { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is64, trap_raz_wi}, /* DBGDSCRext */ { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, trap_debug32, reset_val, cp14_DBGDSCRext, 0 },