| Message ID | 1433438495-16667-2-git-send-email-damien.lespiau@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 04 Jun 2015, Damien Lespiau <damien.lespiau@intel.com> wrote: > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ > drivers/gpu/drm/i915/intel_display.c | 13 ++++++++++++- > 2 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0f72c0e..cfe262c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5761,6 +5761,13 @@ enum skl_disp_power_wells { > #define HSW_NDE_RSTWRN_OPT 0x46408 > #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) > > +#define SKL_DFSM 0x51000 > +#define SKL_DFSM_CDCLK_LIMIT_MASK (0x3 << 23) > +#define SKL_DFSM_CDCLK_LIMIT_675 ( 0 << 23) > +#define SKL_DFSM_CDCLK_LIMIT_540 ( 1 << 23) > +#define SKL_DFSM_CDCLK_LIMIT_450 ( 2 << 23) > +#define SKL_DFSM_CDCLK_LIMIT_337_5 ( 3 << 23) Removed the spaces after ( while applying due to checkpatch whine. BR, Jani. > + > #define FF_SLICE_CS_CHICKEN2 0x20e4 > #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a96f181..6989626 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5631,7 +5631,18 @@ static void intel_update_max_cdclk(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (IS_BROADWELL(dev)) { > + if (IS_SKYLAKE(dev)) { > + u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; > + > + if (limit == SKL_DFSM_CDCLK_LIMIT_675) > + dev_priv->max_cdclk_freq = 675000; > + else if (limit == SKL_DFSM_CDCLK_LIMIT_540) > + dev_priv->max_cdclk_freq = 540000; > + else if (limit == SKL_DFSM_CDCLK_LIMIT_450) > + dev_priv->max_cdclk_freq = 450000; > + else > + dev_priv->max_cdclk_freq = 337500; > + } else if (IS_BROADWELL(dev)) { > /* > * FIXME with extra cooling we can allow > * 540 MHz for ULX and 675 Mhz for ULT. > -- > 2.1.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0f72c0e..cfe262c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5761,6 +5761,13 @@ enum skl_disp_power_wells { #define HSW_NDE_RSTWRN_OPT 0x46408 #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) +#define SKL_DFSM 0x51000 +#define SKL_DFSM_CDCLK_LIMIT_MASK (0x3 << 23) +#define SKL_DFSM_CDCLK_LIMIT_675 ( 0 << 23) +#define SKL_DFSM_CDCLK_LIMIT_540 ( 1 << 23) +#define SKL_DFSM_CDCLK_LIMIT_450 ( 2 << 23) +#define SKL_DFSM_CDCLK_LIMIT_337_5 ( 3 << 23) + #define FF_SLICE_CS_CHICKEN2 0x20e4 #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a96f181..6989626 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5631,7 +5631,18 @@ static void intel_update_max_cdclk(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (IS_BROADWELL(dev)) { + if (IS_SKYLAKE(dev)) { + u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; + + if (limit == SKL_DFSM_CDCLK_LIMIT_675) + dev_priv->max_cdclk_freq = 675000; + else if (limit == SKL_DFSM_CDCLK_LIMIT_540) + dev_priv->max_cdclk_freq = 540000; + else if (limit == SKL_DFSM_CDCLK_LIMIT_450) + dev_priv->max_cdclk_freq = 450000; + else + dev_priv->max_cdclk_freq = 337500; + } else if (IS_BROADWELL(dev)) { /* * FIXME with extra cooling we can allow * 540 MHz for ULX and 675 Mhz for ULT.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ drivers/gpu/drm/i915/intel_display.c | 13 ++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-)