diff mbox

[v3,2/6] drm/i915/gen8: Re-order init pipe_control in lrc mode

Message ID 1433512539-7382-1-git-send-email-arun.siluvery@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

arun.siluvery@linux.intel.com June 5, 2015, 1:55 p.m. UTC 
Some of the WA applied using WA batch buffers perform writes to scratch page.
In the current flow WA are initialized before scratch obj is allocated.
This patch reorders intel_init_pipe_control() to have a valid scratch obj
before we initialize WA.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4e68b54..68df878 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1602,6 +1602,10 @@  static int logical_render_ring_init(struct drm_device *dev)
 
 	ring->dev = dev;
 
+	ret = intel_init_pipe_control(ring);
+	if (ret)
+		return ret;
+
 	if (INTEL_INFO(ring->dev)->gen >= 8) {
 		ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE);
 		if (ret) {
@@ -1622,10 +1626,6 @@  static int logical_render_ring_init(struct drm_device *dev)
 	if (ret)
 		goto clear_wa_ctx;
 
-	ret = intel_init_pipe_control(ring);
-	if (ret)
-		goto clear_wa_ctx;
-
 	return 0;
 
 clear_wa_ctx: