| Message ID | 1434029476-958-2-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 06/11/2015 06:31 AM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV > docs got updated at some point to say that we need to align them to > 128k, just like we do on gen4. > > So far I've seen the problem manifest when the stride is an odd multiple > of 512 bytes, and the surface address meets the following pattern > '(addr & 0xf000) == 0x1000' (also == 0x2000 is problematic on VLV). The > result is a starcase effect (so some pages get dropped maybe?), with a > few pages here and there clearly getting scannout out at the wrong position. > > I've not actually been able to reproduce this problem on gen4, so it's > not clear of the issue is any way related to the 128k restrictions > supposedly inherited from gen4. But let's hope the 128k alignment is > sufficient to hide it all. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 0ac213a..2221323 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2329,7 +2329,8 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) > { > if (INTEL_INFO(dev_priv)->gen >= 9) > return 256 * 1024; > - else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv)) > + else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || > + IS_VALLEYVIEW(dev_priv)) > return 128 * 1024; > else if (INTEL_INFO(dev_priv)->gen >= 4) > return 4 * 1024; > Fairly straight forward now that we know VLV and CHV require the 128k alignment. Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
On Thursday 11 June 2015 07:01 PM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV > docs got updated at some point to say that we need to align them to > 128k, just like we do on gen4. > > So far I've seen the problem manifest when the stride is an odd multiple > of 512 bytes, and the surface address meets the following pattern > '(addr & 0xf000) == 0x1000' (also == 0x2000 is problematic on VLV). The > result is a starcase effect (so some pages get dropped maybe?), with a > few pages here and there clearly getting scannout out at the wrong position. > > I've not actually been able to reproduce this problem on gen4, so it's > not clear of the issue is any way related to the 128k restrictions > supposedly inherited from gen4. But let's hope the 128k alignment is > sufficient to hide it all. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Thanks and Regards, Arun R Murthy -------------------
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0ac213a..2221323 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2329,7 +2329,8 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) { if (INTEL_INFO(dev_priv)->gen >= 9) return 256 * 1024; - else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv)) + else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || + IS_VALLEYVIEW(dev_priv)) return 128 * 1024; else if (INTEL_INFO(dev_priv)->gen >= 4) return 4 * 1024;