From patchwork Wed Jun 17 11:00:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 6623961 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E27FEC0020 for ; Wed, 17 Jun 2015 11:01:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E6327208C3 for ; Wed, 17 Jun 2015 11:01:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 68CEC208BE for ; Wed, 17 Jun 2015 11:01:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4DEA86E1DC; Wed, 17 Jun 2015 04:01:12 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 197DD6E1DC for ; Wed, 17 Jun 2015 04:01:11 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 17 Jun 2015 04:00:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,632,1427785200"; d="scan'208";a="745058104" Received: from ideak-desk.fi.intel.com ([10.237.72.74]) by fmsmga002.fm.intel.com with ESMTP; 17 Jun 2015 04:00:55 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Wed, 17 Jun 2015 14:00:54 +0300 Message-Id: <1434538855-21722-1-git-send-email-imre.deak@intel.com> X-Mailer: git-send-email 2.1.4 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: factor out intel_mode_target_cdclk X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For GEN9 the target cdclk frequency is needed during the modeset state check phase too, so factor out this functionality. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_display.c | 48 ++++++++++++++++++++++-------------- 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2641053..9b68a5c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5899,21 +5899,37 @@ static int intel_mode_max_pixclk(struct drm_device *dev, return max_pixclk; } -static int valleyview_modeset_global_pipes(struct drm_atomic_state *state) +static int intel_mode_target_cdclk(struct drm_i915_private *dev_priv, + struct drm_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->dev); - struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; - int max_pixclk = intel_mode_max_pixclk(state->dev, state); - int cdclk, ret = 0; + int max_pixclk = intel_mode_max_pixclk(dev_priv->dev, state); + int cdclk; if (max_pixclk < 0) return max_pixclk; - if (IS_VALLEYVIEW(dev_priv)) - cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); - else + if (IS_BROXTON(dev_priv)) { cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); + } else if (IS_VALLEYVIEW(dev_priv)) { + cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); + } else { + MISSING_CASE(INTEL_INFO(dev_priv)); + cdclk = 0; + } + + return cdclk; +} + +static int valleyview_modeset_global_pipes(struct drm_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->dev); + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + int cdclk, ret = 0; + + cdclk = intel_mode_target_cdclk(dev_priv, state); + if (cdclk < 0) + return cdclk; if (cdclk == dev_priv->cdclk_freq) return 0; @@ -5981,16 +5997,14 @@ static void valleyview_modeset_global_resources(struct drm_atomic_state *old_sta { struct drm_device *dev = old_state->dev; struct drm_i915_private *dev_priv = dev->dev_private; - int max_pixclk = intel_mode_max_pixclk(dev, NULL); int req_cdclk; - /* The path in intel_mode_max_pixclk() with a NULL atomic state should + /* The path in intel_mode_target_cdclk() with a NULL atomic state should * never fail. */ - if (WARN_ON(max_pixclk < 0)) + req_cdclk = intel_mode_target_cdclk(dev_priv, NULL); + if (WARN_ON(req_cdclk < 0)) return; - req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); - if (req_cdclk != dev_priv->cdclk_freq) { /* * FIXME: We can end up here with all power domains off, yet @@ -9556,15 +9570,13 @@ static void broxton_modeset_global_resources(struct drm_atomic_state *old_state) { struct drm_device *dev = old_state->dev; struct drm_i915_private *dev_priv = dev->dev_private; - int max_pixclk = intel_mode_max_pixclk(dev, NULL); int req_cdclk; /* see the comment in valleyview_modeset_global_resources */ - if (WARN_ON(max_pixclk < 0)) + req_cdclk = intel_mode_target_cdclk(dev_priv, NULL); + if (WARN_ON(req_cdclk < 0)) return; - req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); - if (req_cdclk != dev_priv->cdclk_freq) broxton_set_cdclk(dev, req_cdclk); }