[2/2] drm/i915/bxt: fix max scaling factor calculation
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Message ID 1434538855-21722-2-git-send-email-imre.deak@intel.com
State New
Headers show

Commit Message

Imre Deak June 17, 2015, 11 a.m. UTC
Atm when calculating the maximum plane scale factor, we use the active
CDCLK rate. The target CDCLK rate for the upcoming modeset may be
different from this, so use the target rate instead.

This fixes the modeset on BXT, where the initial rate was smaller than
the target rate. On SKL we use a fixed CDCLK rate for now, so there this
wasn't an issue.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Patch
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9b68a5c..15b9208 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5908,7 +5908,10 @@  static int intel_mode_target_cdclk(struct drm_i915_private *dev_priv,
 	if (max_pixclk < 0)
 		return max_pixclk;
 
-	if (IS_BROXTON(dev_priv)) {
+	if (IS_SKYLAKE(dev_priv)) {
+		/* FIXME: calculate the actual target clock rate */
+		cdclk = dev_priv->display.get_display_clock_speed(dev_priv->dev);
+	} else if (IS_BROXTON(dev_priv)) {
 		cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
@@ -13597,7 +13600,7 @@  skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
 	dev = intel_crtc->base.dev;
 	dev_priv = dev->dev_private;
 	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
-	cdclk = dev_priv->display.get_display_clock_speed(dev);
+	cdclk = intel_mode_target_cdclk(dev_priv, crtc_state->base.state);
 
 	if (!crtc_clock || !cdclk)
 		return DRM_PLANE_HELPER_NO_SCALING;