[v2,4/9] clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant

Commit Message

Heiko Stuebner June 18, 2015, 2:18 p.m. UTC

A clock branch consisting of a mux and divider with non-standard
divider values.

Signed-off-by: Heiko Stuebner <[e-mail]>
---
 drivers/clk/rockchip/clk.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Stephen Boyd July 2, 2015, 10:52 p.m. UTC | #1

On 06/18, Heiko Stuebner wrote:
> A clock branch consisting of a mux and divider with non-standard
> divider values.
> 
> Signed-off-by: Heiko Stuebner <[e-mail]>
> ---

Applied to clk-rk3368. The rest of the series needs a respin.

Patch

diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 92edb5f..501f02e 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -308,6 +308,26 @@  struct rockchip_clk_branch {
 		.gate_offset	= -1,				\
 	}
 
+#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,	\
+				mw, mf, ds, dw, df, dt)		\
+	{							\
+		.id		= _id,				\
+		.branch_type	= branch_composite,		\
+		.name		= cname,			\
+		.parent_names	= pnames,			\
+		.num_parents	= ARRAY_SIZE(pnames),		\
+		.flags		= f,				\
+		.muxdiv_offset	= mo,				\
+		.mux_shift	= ms,				\
+		.mux_width	= mw,				\
+		.mux_flags	= mf,				\
+		.div_shift	= ds,				\
+		.div_width	= dw,				\
+		.div_flags	= df,				\
+		.div_table	= dt,				\
+		.gate_offset	= -1,				\
+	}
+
 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
 	{							\
 		.id		= _id,				\