drm/i915: Add the ddi get cdclk code for BXT (v2)
diff mbox

Message ID 1434645485-23304-1-git-send-email-matthew.d.roper@intel.com
State New
Headers show

Commit Message

Matt Roper June 18, 2015, 4:38 p.m. UTC
From: Bob Paauwe <bob.j.paauwe@intel.com>

The registers and process differ from other platforms.

v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

Comments

Ville Syrjälä June 22, 2015, 1:26 p.m. UTC | #1
On Thu, Jun 18, 2015 at 09:38:05AM -0700, Matt Roper wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
> 
> The registers and process differ from other platforms.
> 
> v2(Matt): Return 19.2 MHz when DE PLL is disabled (Ville)
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3ee7dbc..294c4e4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6689,6 +6689,34 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
>  	return 24000;
>  }
>  
> +static int broxton_get_display_clock_speed(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	uint32_t cdctl = I915_READ(CDCLK_CTL);
> +	uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
> +	uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
> +
> +	if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
> +		return 19200;
> +
> +	switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
> +	case BXT_CDCLK_CD2X_DIV_SEL_1:
> +		if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
> +			return 576000;
> +		else /* PLL freq = 1248MHz */
> +			return 624000;
> +	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> +		return 384000;
> +	case BXT_CDCLK_CD2X_DIV_SEL_2:
> +		return 288000;
> +	case BXT_CDCLK_CD2X_DIV_SEL_4:
> +		return 144000;
> +	}

I'd try write this in a way that makes less assumptions about the
hardware state, so that it would also catch misprogramming.
Maybe something like this:

freq = 19200 * (pll_freq & BXT_DE_PLL_RATIO_MASK) / 2;
switch (...) {
case BXT_CDCLK_CD2X_DIV_SEL_1:
	return freq;
case BXT_CDCLK_CD2X_DIV_SEL_1_5:
	return freq * 3 / 2;
...


> +
> +	/* error case, assume higer PLL freq. */
> +	return 624000;
> +}
> +
>  static int broadwell_get_display_clock_speed(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -14715,6 +14743,9 @@ static void intel_init_display(struct drm_device *dev)
>  	if (IS_SKYLAKE(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			skylake_get_display_clock_speed;
> +	else if (IS_BROXTON(dev))
> +		dev_priv->display.get_display_clock_speed =
> +			broxton_get_display_clock_speed;
>  	else if (IS_BROADWELL(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			broadwell_get_display_clock_speed;
> -- 
> 1.8.5.1

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3ee7dbc..294c4e4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6689,6 +6689,34 @@  static int skylake_get_display_clock_speed(struct drm_device *dev)
 	return 24000;
 }
 
+static int broxton_get_display_clock_speed(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	uint32_t cdctl = I915_READ(CDCLK_CTL);
+	uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
+	uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
+
+	if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
+		return 19200;
+
+	switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
+	case BXT_CDCLK_CD2X_DIV_SEL_1:
+		if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
+			return 576000;
+		else /* PLL freq = 1248MHz */
+			return 624000;
+	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
+		return 384000;
+	case BXT_CDCLK_CD2X_DIV_SEL_2:
+		return 288000;
+	case BXT_CDCLK_CD2X_DIV_SEL_4:
+		return 144000;
+	}
+
+	/* error case, assume higer PLL freq. */
+	return 624000;
+}
+
 static int broadwell_get_display_clock_speed(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -14715,6 +14743,9 @@  static void intel_init_display(struct drm_device *dev)
 	if (IS_SKYLAKE(dev))
 		dev_priv->display.get_display_clock_speed =
 			skylake_get_display_clock_speed;
+	else if (IS_BROXTON(dev))
+		dev_priv->display.get_display_clock_speed =
+			broxton_get_display_clock_speed;
 	else if (IS_BROADWELL(dev))
 		dev_priv->display.get_display_clock_speed =
 			broadwell_get_display_clock_speed;