From patchwork Tue Jun 23 01:30:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 6658641 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 40271C05AC for ; Tue, 23 Jun 2015 01:31:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2DF95205CD for ; Tue, 23 Jun 2015 01:31:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 58C7D2058A for ; Tue, 23 Jun 2015 01:31:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DB20D6E5ED; Mon, 22 Jun 2015 18:31:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 6A8C56E5ED for ; Mon, 22 Jun 2015 18:31:12 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 22 Jun 2015 18:31:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,663,1427785200"; d="scan'208";a="715859576" Received: from mdroper-hswdev.fm.intel.com (HELO mdroper-hswdev) ([10.1.134.215]) by orsmga001.jf.intel.com with ESMTP; 22 Jun 2015 18:31:10 -0700 Received: from mattrope by mdroper-hswdev with local (Exim 4.84) (envelope-from ) id 1Z7D3O-0004hw-E0; Mon, 22 Jun 2015 18:31:10 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Jun 2015 18:30:32 -0700 Message-Id: <1435023033-18043-2-git-send-email-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1435023033-18043-1-git-send-email-matthew.d.roper@intel.com> References: <1435023033-18043-1-git-send-email-matthew.d.roper@intel.com> Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Drop parameters to intel_update_sprite_watermarks() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The values that ultimately get passed to intel_update_sprite_watermarks() are pulled out of the plane state (which has already been swapped into plane->state) as we update the plane programming. Drop the function parameters and just pull the relevant values out of the state structure inside the function. This change will make it easier for a future patch to pull the sprite WM programming out of the low-level foo_update_plane() functions (which are run under vblank evasion and shouldn't be calling potentially blocking watermark functions). Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/intel_display.c | 3 +-- drivers/gpu/drm/i915/intel_drv.h | 6 +----- drivers/gpu/drm/i915/intel_pm.c | 17 ++++++++++++----- drivers/gpu/drm/i915/intel_sprite.c | 21 ++++++--------------- 4 files changed, 20 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index de6f8cc..5e8e01c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4719,8 +4719,7 @@ static void intel_post_plane_update(struct intel_crtc *crtc) intel_post_enable_primary(&crtc->base); drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks) - intel_update_sprite_watermarks(plane, &crtc->base, - 0, 0, 0, false, false); + intel_update_sprite_watermarks(plane, &crtc->base); memset(atomic, 0, sizeof(*atomic)); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index e2174fd..fdfa2c9 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1355,11 +1355,7 @@ void intel_suspend_hw(struct drm_device *dev); int ilk_wm_max_level(const struct drm_device *dev); void intel_update_watermarks(struct drm_crtc *crtc); void intel_update_sprite_watermarks(struct drm_plane *plane, - struct drm_crtc *crtc, - uint32_t sprite_width, - uint32_t sprite_height, - int pixel_size, - bool enabled, bool scaled); + struct drm_crtc *crtc); void intel_init_pm(struct drm_device *dev); void intel_pm_setup(struct drm_device *dev); void intel_gpu_ips_init(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 32ff034..4d3cb70 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3755,13 +3755,20 @@ void intel_update_watermarks(struct drm_crtc *crtc) } void intel_update_sprite_watermarks(struct drm_plane *plane, - struct drm_crtc *crtc, - uint32_t sprite_width, - uint32_t sprite_height, - int pixel_size, - bool enabled, bool scaled) + struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = plane->dev->dev_private; + struct intel_plane_state *state = to_intel_plane_state(plane->state); + struct drm_framebuffer *fb = state->base.fb; + uint32_t sprite_width = drm_rect_width(&state->dst); + uint32_t sprite_height = drm_rect_height(&state->dst); + int pixel_size = fb ? drm_format_plane_cpp(fb->pixel_format, 0) : 0; + bool enabled = state->visible; + unsigned int src_w = drm_rect_width(&state->src) >> 16; + unsigned int src_h = drm_rect_height(&state->src) >> 16; + unsigned int dst_w = drm_rect_width(&state->dst); + unsigned int dst_h = drm_rect_height(&state->dst); + bool scaled = (src_w != dst_w || src_h != dst_h); if (dev_priv->display.update_sprite_wm) dev_priv->display.update_sprite_wm(plane, crtc, diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index e0045aa..b627067 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -181,7 +181,6 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, const int pipe = intel_plane->pipe; const int plane = intel_plane->plane + 1; u32 plane_ctl, stride_div, stride; - int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); const struct drm_intel_sprite_colorkey *key = &to_intel_plane_state(drm_plane->state)->ckey; unsigned long surf_addr; @@ -200,9 +199,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, rotation = drm_plane->state->rotation; plane_ctl |= skl_plane_ctl_rotation(rotation); - intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h, - pixel_size, true, - src_w != crtc_w || src_h != crtc_h); + intel_update_sprite_watermarks(drm_plane, crtc); stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], fb->pixel_format); @@ -286,7 +283,7 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) I915_WRITE(PLANE_SURF(pipe, plane), 0); POSTING_READ(PLANE_SURF(pipe, plane)); - intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); + intel_update_sprite_watermarks(dplane, crtc); } static void @@ -402,9 +399,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, if (obj->tiling_mode != I915_TILING_NONE) sprctl |= SP_TILED; - intel_update_sprite_watermarks(dplane, crtc, src_w, src_h, - pixel_size, true, - src_w != crtc_w || src_h != crtc_h); + intel_update_sprite_watermarks(dplane, crtc); /* Sizes are 0 based */ src_w--; @@ -471,7 +466,7 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) I915_WRITE(SPSURF(pipe, plane), 0); POSTING_READ(SPSURF(pipe, plane)); - intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); + intel_update_sprite_watermarks(dplane, crtc); } static void @@ -535,9 +530,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, if (IS_HASWELL(dev) || IS_BROADWELL(dev)) sprctl |= SPRITE_PIPE_CSC_ENABLE; - intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size, - true, - src_w != crtc_w || src_h != crtc_h); + intel_update_sprite_watermarks(plane, crtc); /* Sizes are 0 based */ src_w--; @@ -672,9 +665,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, if (IS_GEN6(dev)) dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ - intel_update_sprite_watermarks(plane, crtc, src_w, src_h, - pixel_size, true, - src_w != crtc_w || src_h != crtc_h); + intel_update_sprite_watermarks(plane, crtc); /* Sizes are 0 based */ src_w--;