[1/2] drm/i915: Fix warnings reported by 0-day
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Message ID 1435071044-34640-2-git-send-email-arun.siluvery@linux.intel.com
State New
Headers show

Commit Message

arun.siluvery@linux.intel.com June 23, 2015, 2:50 p.m. UTC
Kernel 0-day framework reported warnings with WA batch patches, this patch
fixes those warnings and an additional warning reported in intel_lrc.c file.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Patch
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diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e4ebe05..6bfa2f1 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -784,6 +784,7 @@  static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
  * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
  *
  * @request: The request to start some new work for
+ * @ctx: Logical ring context whose ringbuffer is being prepared.
  * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
  *
  * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
@@ -1132,7 +1133,7 @@  static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
  *
  *  The number of WA applied are not known at the beginning; we use this field
  *  to return the no of DWORDS written.
-
+ *
  *  It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
  *  so it adds NOOPs as padding to make it cacheline aligned.
  *  MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
@@ -1209,6 +1210,7 @@  static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring,
  * @wa_ctx: structure representing wa_ctx
  *  offset: specifies start of the batch, should be cache-aligned.
  *  size: size of the batch in DWORDS but HW expects in terms of cachelines
+ * @batch: page in which WA are loaded
  * @offset: This field specifies the start of this batch.
  *   This batch is started immediately after indirect_ctx batch. Since we ensure
  *   that indirect_ctx ends on a cacheline this batch is aligned automatically.