[01/10] drm/i915: POSTING_READ() in intel_set_memory_cxsr()
diff mbox

Message ID 1435172410-9834-2-git-send-email-ville.syrjala@linux.intel.com
State New
Headers show

Commit Message

Ville Syrjälä June 24, 2015, 7 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We want cxsr exit to happen ASAP, so toss in some POSTING_READ()s to
make sure things are really kicked off.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Clinton Taylor June 26, 2015, 8:22 p.m. UTC | #1 
On 06/24/2015 12:00 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We want cxsr exit to happen ASAP, so toss in some POSTING_READ()s to
> make sure things are really kicked off.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 32ff034..9706275 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -334,22 +334,27 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
>
>   	if (IS_VALLEYVIEW(dev)) {
>   		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> +		POSTING_READ(FW_BLC_SELF_VLV);
>   		if (IS_CHERRYVIEW(dev))
>   			chv_set_memory_pm5(dev_priv, enable);
>   	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
>   		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
> +		POSTING_READ(FW_BLC_SELF);
>   	} else if (IS_PINEVIEW(dev)) {
>   		val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
>   		val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
>   		I915_WRITE(DSPFW3, val);
> +		POSTING_READ(DSPFW3);
>   	} else if (IS_I945G(dev) || IS_I945GM(dev)) {
>   		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
>   			       _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
>   		I915_WRITE(FW_BLC_SELF, val);
> +		POSTING_READ(FW_BLC_SELF);
>   	} else if (IS_I915GM(dev)) {
>   		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
>   			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
>   		I915_WRITE(INSTPM, val);
> +		POSTING_READ(INSTPM);
>   	} else {
>   		return;
>   	}
>

Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Tested-by: Clint Taylor <Clinton.A.Taylor@intel.com>

Patch
diff mbox 

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32ff034..9706275 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -334,22 +334,27 @@  void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 
 	if (IS_VALLEYVIEW(dev)) {
 		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
+		POSTING_READ(FW_BLC_SELF_VLV);
 		if (IS_CHERRYVIEW(dev))
 			chv_set_memory_pm5(dev_priv, enable);
 	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
+		POSTING_READ(FW_BLC_SELF);
 	} else if (IS_PINEVIEW(dev)) {
 		val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 		val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 		I915_WRITE(DSPFW3, val);
+		POSTING_READ(DSPFW3);
 	} else if (IS_I945G(dev) || IS_I945GM(dev)) {
 		val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 			       _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 		I915_WRITE(FW_BLC_SELF, val);
+		POSTING_READ(FW_BLC_SELF);
 	} else if (IS_I915GM(dev)) {
 		val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 			       _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 		I915_WRITE(INSTPM, val);
+		POSTING_READ(INSTPM);
 	} else {
 		return;
 	}