Message ID | 1435172410-9834-9-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On 06/24/2015 12:00 PM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Enabling PM5/DDR DVFS with multiple active pipes isn't a validated > configuration. It does seem to work most of the time at least, but > there is clearly an additional risk of underruns, so let's not play > with fire. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index b65817d..c8e7ef3 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1327,6 +1327,9 @@ static void vlv_merge_wm(struct drm_device *dev, > if (num_active_crtcs != 1) > wm->cxsr = false; > > + if (num_active_crtcs > 1) > + wm->level = VLV_WM_LEVEL_PM2; > + > for_each_intel_crtc(dev, crtc) { > struct vlv_wm_state *wm_state = &crtc->wm_state; > enum pipe pipe = crtc->pipe; > Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Tested-by: Clint Taylor <Clinton.A.Taylor@intel.com>
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b65817d..c8e7ef3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1327,6 +1327,9 @@ static void vlv_merge_wm(struct drm_device *dev, if (num_active_crtcs != 1) wm->cxsr = false; + if (num_active_crtcs > 1) + wm->level = VLV_WM_LEVEL_PM2; + for_each_intel_crtc(dev, crtc) { struct vlv_wm_state *wm_state = &crtc->wm_state; enum pipe pipe = crtc->pipe;