[10/10] drm/i915: Zero unused WM1 watermarks on VLV/CHV
diff mbox

Message ID 1435172410-9834-11-git-send-email-ville.syrjala@linux.intel.com
State New
Headers show

Commit Message

Ville Syrjälä June 24, 2015, 7 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The hardware supposedly ignores the WM1 watermarks while the PND
deadline mode is enabled, but clear out the register just in case.
This is what the other OS does, and it does make register dumps look
more consistent when we don't have partial WM1 values lingering in
the registers (some WM1 watermarks already get zeroed when the actually
used DSPFW registers get written).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Clinton Taylor June 26, 2015, 8:24 p.m. UTC | #1
On 06/24/2015 12:00 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The hardware supposedly ignores the WM1 watermarks while the PND
> deadline mode is enabled, but clear out the register just in case.
> This is what the other OS does, and it does make register dumps look
> more consistent when we don't have partial WM1 values lingering in
> the registers (some WM1 watermarks already get zeroed when the actually
> used DSPFW registers get written).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c8e7ef3..dc8a9c9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -927,6 +927,12 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
>   			   FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
>   	}
>
> +	/* zero (unused) WM1 watermarks */
> +	I915_WRITE(DSPFW4, 0);
> +	I915_WRITE(DSPFW5, 0);
> +	I915_WRITE(DSPFW6, 0);
> +	I915_WRITE(DSPHOWM1, 0);
> +
>   	POSTING_READ(DSPFW1);
>   }
>
>

Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Tested-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Daniel Vetter June 29, 2015, 9 a.m. UTC | #2
On Fri, Jun 26, 2015 at 01:24:17PM -0700, Clint Taylor wrote:
> On 06/24/2015 12:00 PM, ville.syrjala@linux.intel.com wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >The hardware supposedly ignores the WM1 watermarks while the PND
> >deadline mode is enabled, but clear out the register just in case.
> >This is what the other OS does, and it does make register dumps look
> >more consistent when we don't have partial WM1 values lingering in
> >the registers (some WM1 watermarks already get zeroed when the actually
> >used DSPFW registers get written).
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> >  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index c8e7ef3..dc8a9c9 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -927,6 +927,12 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
> >  			   FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
> >  	}
> >
> >+	/* zero (unused) WM1 watermarks */
> >+	I915_WRITE(DSPFW4, 0);
> >+	I915_WRITE(DSPFW5, 0);
> >+	I915_WRITE(DSPFW6, 0);
> >+	I915_WRITE(DSPHOWM1, 0);
> >+
> >  	POSTING_READ(DSPFW1);
> >  }
> >
> >
> 
> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>

Pulled in entire series, thanks for patches&review.
-Daniel

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c8e7ef3..dc8a9c9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -927,6 +927,12 @@  static void vlv_write_wm_values(struct intel_crtc *crtc,
 			   FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 	}
 
+	/* zero (unused) WM1 watermarks */
+	I915_WRITE(DSPFW4, 0);
+	I915_WRITE(DSPFW5, 0);
+	I915_WRITE(DSPFW6, 0);
+	I915_WRITE(DSPHOWM1, 0);
+
 	POSTING_READ(DSPFW1);
 }