| Message ID | 1435317536-15362-1-git-send-email-jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6566
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
ILK 303/303 303/303
SNB 312/312 312/312
IVB 343/343 343/343
BYT -1 284/284 283/284
HSW 380/380 380/380
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*BYT igt@gem_partial_pwrite_pread@reads-display PASS(1) FAIL(1)
Note: You need to pay more attention to line start with '*'
On Fri, 26 Jun 2015, Jani Nikula <jani.nikula@intel.com> wrote: > Some 855gm models (at least ThinkPad X40) regressed because of > > commit b0cd324faed23d10d66ba6ade66579c681feef6f > Author: Jani Nikula <jani.nikula@intel.com> > Date: Wed Nov 12 16:25:43 2014 +0200 > > drm/i915: don't save/restore backlight hist ctl registers > > which tried to make our driver more robust by not blindly saving and > restoring registers, but it failed to take into account > > commit 0eb96d6ed38430b72897adde58f5477a6b71757a > Author: Jesse Barnes <jbarnes@virtuousgeek.org> > Date: Wed Oct 14 12:33:41 2009 -0700 > > drm/i915: save/restore BLC histogram control reg across suspend/resume > > Fix the regression by enabling hist ctl on gen2. > > v2: Improved the comment. > > v3: Improved the comment, again. > > Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net> > References: http://mid.gmane.org/20150623222648.GD12335@acheron > Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers") > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: stable@vger.kernel.org > Acked-by: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Pushed to drm-intel-next-fixes, assuming Chris' ack and Philipp's tested-by are enough. BR, Jani. > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_panel.c | 8 ++++++++ > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index fa9ccb87eb66..bf7c08b94088 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3507,6 +3507,7 @@ enum skl_disp_power_wells { > #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ > > #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) > +#define BLM_HISTOGRAM_ENABLE (1 << 31) > > /* New registers for PCH-split platforms. Safe where new bits show up, the > * register layout machtes with gen4 BLC_PWM_CTL[12]. */ > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c > index 7d83527f95f7..55aad2322e10 100644 > --- a/drivers/gpu/drm/i915/intel_panel.c > +++ b/drivers/gpu/drm/i915/intel_panel.c > @@ -907,6 +907,14 @@ static void i9xx_enable_backlight(struct intel_connector *connector) > > /* XXX: combine this into above write? */ > intel_panel_actually_set_backlight(connector, panel->backlight.level); > + > + /* > + * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is > + * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2 > + * that has backlight. > + */ > + if (IS_GEN2(dev)) > + I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); > } > > static void i965_enable_backlight(struct intel_connector *connector) > -- > 2.1.4 >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fa9ccb87eb66..bf7c08b94088 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3507,6 +3507,7 @@ enum skl_disp_power_wells { #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) +#define BLM_HISTOGRAM_ENABLE (1 << 31) /* New registers for PCH-split platforms. Safe where new bits show up, the * register layout machtes with gen4 BLC_PWM_CTL[12]. */ diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 7d83527f95f7..55aad2322e10 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -907,6 +907,14 @@ static void i9xx_enable_backlight(struct intel_connector *connector) /* XXX: combine this into above write? */ intel_panel_actually_set_backlight(connector, panel->backlight.level); + + /* + * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is + * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2 + * that has backlight. + */ + if (IS_GEN2(dev)) + I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); } static void i965_enable_backlight(struct intel_connector *connector)
Some 855gm models (at least ThinkPad X40) regressed because of commit b0cd324faed23d10d66ba6ade66579c681feef6f Author: Jani Nikula <jani.nikula@intel.com> Date: Wed Nov 12 16:25:43 2014 +0200 drm/i915: don't save/restore backlight hist ctl registers which tried to make our driver more robust by not blindly saving and restoring registers, but it failed to take into account commit 0eb96d6ed38430b72897adde58f5477a6b71757a Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Wed Oct 14 12:33:41 2009 -0700 drm/i915: save/restore BLC histogram control reg across suspend/resume Fix the regression by enabling hist ctl on gen2. v2: Improved the comment. v3: Improved the comment, again. Reported-and-tested-by: Philipp Gesang <phg@phi-gamma.net> References: http://mid.gmane.org/20150623222648.GD12335@acheron Fixes: b0cd324faed2 ("drm/i915: don't save/restore backlight hist ctl registers") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: stable@vger.kernel.org Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_panel.c | 8 ++++++++ 2 files changed, 9 insertions(+)