[6/9] drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable
diff mbox

Message ID 1435580756-20154-7-git-send-email-ville.syrjala@linux.intel.com
State New
Headers show

Commit Message

Ville Syrjälä June 29, 2015, 12:25 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Bunch of stuff needs the DPLL ref/cri clocks on both VLV and CHV,
and having VGA mode enabled causes some problems for CHV. So let's just
pull the code to configure those bits into the disp2d well enable hook.
With the DPLL disable code also fixed to leave those bits alone we
should now have a consistent DPLL state all the time even if the DPLL
is disabled.

This also neatly removes some duplicated code between the VLV and
CHV codepaths.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 45 ++++++++++++++++++---------------
 1 file changed, 24 insertions(+), 21 deletions(-)

Comments

Sivakumar Thulasimani July 10, 2015, 12:33 p.m. UTC | #1
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>



On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Bunch of stuff needs the DPLL ref/cri clocks on both VLV and CHV,
> and having VGA mode enabled causes some problems for CHV. So let's just
> pull the code to configure those bits into the disp2d well enable hook.
> With the DPLL disable code also fixed to leave those bits alone we
> should now have a consistent DPLL state all the time even if the DPLL
> is disabled.
>
> This also neatly removes some duplicated code between the VLV and
> CHV codepaths.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_runtime_pm.c | 45 ++++++++++++++++++---------------
>   1 file changed, 24 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6393b76..2142ae6 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -837,6 +837,25 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
>   
>   static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
>   {
> +	enum pipe pipe;
> +
> +	/*
> +	 * Enable the CRI clock source so we can get at the
> +	 * display and the reference clock for VGA
> +	 * hotplug / manual detection. Supposedly DSI also
> +	 * needs the ref clock up and running.
> +	 *
> +	 * CHV DPLL B/C have some issues if VGA mode is enabled.
> +	 */
> +	for_each_pipe(dev_priv->dev, pipe) {
> +		u32 val = I915_READ(DPLL(pipe));
> +
> +		val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> +		if (pipe != PIPE_A)
> +			val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> +
> +		I915_WRITE(DPLL(pipe), val);
> +	}
>   
>   	spin_lock_irq(&dev_priv->irq_lock);
>   	valleyview_enable_display_irqs(dev_priv);
> @@ -888,13 +907,7 @@ static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
>   {
>   	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
>   
> -	/*
> -	 * Enable the CRI clock source so we can get at the
> -	 * display and the reference clock for VGA
> -	 * hotplug / manual detection.
> -	 */
> -	I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
> -		   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
> +	/* since ref/cri clock was enabled */
>   	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
>   
>   	vlv_set_power_well(dev_priv, power_well, true);
> @@ -937,22 +950,12 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
>   	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
>   		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
>   
> -	/*
> -	 * Enable the CRI clock source so we can get at the
> -	 * display and the reference clock for VGA
> -	 * hotplug / manual detection.
> -	 */
> -	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> +	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC)
>   		phy = DPIO_PHY0;
> -		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
> -			   DPLL_REF_CLK_ENABLE_VLV);
> -		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
> -			   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
> -	} else {
> +	else
>   		phy = DPIO_PHY1;
> -		I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS |
> -			   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
> -	}
> +
> +	/* since ref/cri clock was enabled */
>   	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
>   	vlv_set_power_well(dev_priv, power_well, true);
>
Daniel Vetter Aug. 26, 2015, 12:34 p.m. UTC | #2
Queued for -next to resolve conflicts in another series, thanks for the patch.
-Daniel

On Fri, Jul 10, 2015 at 06:03:39PM +0530, Sivakumar Thulasimani wrote:
> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> 
> 
> 
> On 6/29/2015 5:55 PM, ville.syrjala@linux.intel.com wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Bunch of stuff needs the DPLL ref/cri clocks on both VLV and CHV,
> >and having VGA mode enabled causes some problems for CHV. So let's just
> >pull the code to configure those bits into the disp2d well enable hook.
> >With the DPLL disable code also fixed to leave those bits alone we
> >should now have a consistent DPLL state all the time even if the DPLL
> >is disabled.
> >
> >This also neatly removes some duplicated code between the VLV and
> >CHV codepaths.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 45 ++++++++++++++++++---------------
> >  1 file changed, 24 insertions(+), 21 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> >index 6393b76..2142ae6 100644
> >--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> >@@ -837,6 +837,25 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
> >  static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
> >  {
> >+	enum pipe pipe;
> >+
> >+	/*
> >+	 * Enable the CRI clock source so we can get at the
> >+	 * display and the reference clock for VGA
> >+	 * hotplug / manual detection. Supposedly DSI also
> >+	 * needs the ref clock up and running.
> >+	 *
> >+	 * CHV DPLL B/C have some issues if VGA mode is enabled.
> >+	 */
> >+	for_each_pipe(dev_priv->dev, pipe) {
> >+		u32 val = I915_READ(DPLL(pipe));
> >+
> >+		val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> >+		if (pipe != PIPE_A)
> >+			val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> >+
> >+		I915_WRITE(DPLL(pipe), val);
> >+	}
> >  	spin_lock_irq(&dev_priv->irq_lock);
> >  	valleyview_enable_display_irqs(dev_priv);
> >@@ -888,13 +907,7 @@ static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> >  {
> >  	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
> >-	/*
> >-	 * Enable the CRI clock source so we can get at the
> >-	 * display and the reference clock for VGA
> >-	 * hotplug / manual detection.
> >-	 */
> >-	I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
> >-		   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
> >+	/* since ref/cri clock was enabled */
> >  	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
> >  	vlv_set_power_well(dev_priv, power_well, true);
> >@@ -937,22 +950,12 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> >  	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
> >  		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
> >-	/*
> >-	 * Enable the CRI clock source so we can get at the
> >-	 * display and the reference clock for VGA
> >-	 * hotplug / manual detection.
> >-	 */
> >-	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
> >+	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC)
> >  		phy = DPIO_PHY0;
> >-		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
> >-			   DPLL_REF_CLK_ENABLE_VLV);
> >-		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
> >-			   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
> >-	} else {
> >+	else
> >  		phy = DPIO_PHY1;
> >-		I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS |
> >-			   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
> >-	}
> >+
> >+	/* since ref/cri clock was enabled */
> >  	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
> >  	vlv_set_power_well(dev_priv, power_well, true);
> 
> -- 
> regards,
> Sivakumar
> 

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6393b76..2142ae6 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -837,6 +837,25 @@  static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 
 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 {
+	enum pipe pipe;
+
+	/*
+	 * Enable the CRI clock source so we can get at the
+	 * display and the reference clock for VGA
+	 * hotplug / manual detection. Supposedly DSI also
+	 * needs the ref clock up and running.
+	 *
+	 * CHV DPLL B/C have some issues if VGA mode is enabled.
+	 */
+	for_each_pipe(dev_priv->dev, pipe) {
+		u32 val = I915_READ(DPLL(pipe));
+
+		val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
+		if (pipe != PIPE_A)
+			val |= DPLL_INTEGRATED_CRI_CLK_VLV;
+
+		I915_WRITE(DPLL(pipe), val);
+	}
 
 	spin_lock_irq(&dev_priv->irq_lock);
 	valleyview_enable_display_irqs(dev_priv);
@@ -888,13 +907,7 @@  static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 {
 	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 
-	/*
-	 * Enable the CRI clock source so we can get at the
-	 * display and the reference clock for VGA
-	 * hotplug / manual detection.
-	 */
-	I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
-		   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
+	/* since ref/cri clock was enabled */
 	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 
 	vlv_set_power_well(dev_priv, power_well, true);
@@ -937,22 +950,12 @@  static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 	WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
 		     power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
 
-	/*
-	 * Enable the CRI clock source so we can get at the
-	 * display and the reference clock for VGA
-	 * hotplug / manual detection.
-	 */
-	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+	if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC)
 		phy = DPIO_PHY0;
-		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
-			   DPLL_REF_CLK_ENABLE_VLV);
-		I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
-			   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
-	} else {
+	else
 		phy = DPIO_PHY1;
-		I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS |
-			   DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
-	}
+
+	/* since ref/cri clock was enabled */
 	udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 	vlv_set_power_well(dev_priv, power_well, true);