| Message ID | 1435717005-20012-2-git-send-email-pi-cheng.chen@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 01-07-15, 10:16, Pi-Cheng Chen wrote: > This patch adds device tree binding document for MT8173 cpufreq driver. > > Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> > Reviewed-by: Michael Turquette <mturquette@baylibre.com> > --- > .../devicetree/bindings/cpufreq/cpufreq-mt8173.txt | 145 +++++++++++++++++++++ > 1 file changed, 145 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt > new file mode 100644 > index 0000000..65701c5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt > @@ -0,0 +1,145 @@ > + > +Mediatek MT8173 cpufreq driver > +------------------------------ > + > +Mediatek MT8173 cpufreq driver for CPU frequency scaling. > + > +Required properties: > +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. > +- clock-names: Should contain the following: > + "cpu" - The multiplexer for clock input of CPU cluster. > + "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock > + source (usually MAINPLL) when the original CPU PLL is under > + transition and not stable yet. > + Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for > + generic clock consumer properties. Don't have any intentions to halt this series anymore, I have irritated you enough already :) But, what about moving these bindings in something like a clock driver? @Mike: ? I am asking because these really belong to the clock driver, as I understood it from Mike. And clearly asked me to not take care of such things in cpufreq core/drivers. Another reason is that, later you will kill this driver one day and use cpufreq-dt. And then you will be required to move these bindings to a clock driver, as these will stay.
Quoting Viresh Kumar (2015-07-08 04:19:00) > On 01-07-15, 10:16, Pi-Cheng Chen wrote: > > This patch adds device tree binding document for MT8173 cpufreq driver. > > > > Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> > > Reviewed-by: Michael Turquette <mturquette@baylibre.com> > > --- > > .../devicetree/bindings/cpufreq/cpufreq-mt8173.txt | 145 +++++++++++++++++++++ > > 1 file changed, 145 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt > > > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt > > new file mode 100644 > > index 0000000..65701c5 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt > > @@ -0,0 +1,145 @@ > > + > > +Mediatek MT8173 cpufreq driver > > +------------------------------ > > + > > +Mediatek MT8173 cpufreq driver for CPU frequency scaling. > > + > > +Required properties: > > +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. > > +- clock-names: Should contain the following: > > + "cpu" - The multiplexer for clock input of CPU cluster. > > + "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock > > + source (usually MAINPLL) when the original CPU PLL is under > > + transition and not stable yet. > > + Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for > > + generic clock consumer properties. > > Don't have any intentions to halt this series anymore, I have > irritated you enough already :) > > But, what about moving these bindings in something like a clock > driver? > > @Mike: ? Viresh, Pi-Cheng is using the consumer portion of the clock binding, and he is using it correctly. You can see this type of thing sprinkled all over. For instance, many I/O controller do this exact same thing. > > I am asking because these really belong to the clock driver, as I > understood it from Mike. And clearly asked me to not take care of such > things in cpufreq core/drivers. The clock driver is the "provider" and it is separate. This binding is the "consumer". > > Another reason is that, later you will kill this driver one day and > use cpufreq-dt. And then you will be required to move these bindings > to a clock driver, as these will stay. I'm not sure I follow. Again, the use of the consumer side of the clock binding is absolutely correct. Take a quick look at clock-bindings.txt and search for the section titled, "==Clock consumers==" for more info. Regards, Mike > > -- > viresh > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt new file mode 100644 index 0000000..65701c5 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt @@ -0,0 +1,145 @@ + +Mediatek MT8173 cpufreq driver +------------------------------ + +Mediatek MT8173 cpufreq driver for CPU frequency scaling. + +Required properties: +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. +- clock-names: Should contain the following: + "cpu" - The multiplexer for clock input of CPU cluster. + "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock + source (usually MAINPLL) when the original CPU PLL is under + transition and not stable yet. + Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for + generic clock consumer properties. +- operating-points: Please refer to Documentation/devicetree/bindings/power/opp.txt for + details. +- proc-supply: Regulator for Vproc of CPU cluster. + +Optional properties: +- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver + needs to do "voltage trace" to step by step scale up/down Vproc and + Vsram to fit SoC specific needs. When absent, the voltage scaling + flow is handled by hardware, hence no software "voltage trace" is + needed. +- #cooling-cells: +- cooling-min-level: +- cooling-max-level: + Please refer to Documentation/devicetree/bindings/thermal/thermal.txt. + +Example: +-------- + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 859000 + 702000 908000 + 1001000 983000 + 1105000 1009000 + 1183000 1028000 + 1404000 1083000 + 1508000 1109000 + 1573000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x001>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 859000 + 702000 908000 + 1001000 983000 + 1105000 1009000 + 1183000 1028000 + 1404000 1083000 + 1508000 1109000 + 1573000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA57SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 828000 + 702000 867000 + 1001000 927000 + 1209000 968000 + 1404000 1007000 + 1612000 1049000 + 1807000 1089000 + 1989000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA57SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points = < + 507000 828000 + 702000 867000 + 1001000 927000 + 1209000 968000 + 1404000 1007000 + 1612000 1049000 + 1807000 1089000 + 1989000 1125000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; + }; + + &cpu0 { + proc-supply = <&mt6397_vpca15_reg>; + }; + + &cpu1 { + proc-supply = <&mt6397_vpca15_reg>; + }; + + &cpu2 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; + }; + + &cpu3 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; + };