From patchwork Wed Jul 1 19:13:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 6706261 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7D67DC05AC for ; Wed, 1 Jul 2015 19:13:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5B42F206ED for ; Wed, 1 Jul 2015 19:13:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2FB30206EB for ; Wed, 1 Jul 2015 19:13:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 51C14892CD; Wed, 1 Jul 2015 12:13:53 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 0EF4B892CD for ; Wed, 1 Jul 2015 12:13:51 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 01 Jul 2015 12:13:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,388,1432623600"; d="scan'208";a="756749835" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.88]) by orsmga002.jf.intel.com with SMTP; 01 Jul 2015 12:13:49 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 01 Jul 2015 22:13:38 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Jul 2015 22:13:38 +0300 Message-Id: <1435778018-9412-1-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.3.6 In-Reply-To: <1435172410-9834-8-git-send-email-ville.syrjala@linux.intel.com> References: <1435172410-9834-8-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH v2 07/10] drm/i915: Try to make sure cxsr is disabled around plane enable/disable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä CxSR (or maxfifo on VLV/CHV) blocks somne changes to the plane control register (enable bit at least, not quite sure about the rest). So in order to have the plane enable/disable when we want we need to first kick the hardware out of cxsr. Unfortunateloy this requires some extra vblank waits. For the CxSR enable after the plane update we should eventually use an async vblank worker, but since we don't have that just do sync vblank waits. For the disable case we have no choice but to do it synchronously. v2: Don't add a spurious intel_pre_plane_update() to crtc disable Cc: Paulo Zanoni Reviewed-by: Clint Taylor Tested-by: Clint Taylor Signed-off-by: Ville Syrjälä Tested-by: Matt Roper --- Paulo noticed some frontbuffer_bits WARNs from this patch, and sure enough I accidentally added another intel_pre_plane_update() to the crtc disable loop. I failed to notice because I had commented out the frontbuffer_bits WARNs earlier from my tree since they were too noisy. drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_drv.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 11 ++++------- 3 files changed, 36 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d67b5f1..defc4ce 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4716,6 +4716,9 @@ static void intel_post_plane_update(struct intel_crtc *crtc) intel_frontbuffer_flip(dev, atomic->fb_bits); + if (atomic->disable_cxsr) + crtc->wm.cxsr_allowed = true; + if (crtc->atomic.update_wm_post) intel_update_watermarks(&crtc->base); @@ -4765,6 +4768,11 @@ static void intel_pre_plane_update(struct intel_crtc *crtc) if (atomic->pre_disable_primary) intel_pre_disable_primary(&crtc->base); + + if (atomic->disable_cxsr) { + crtc->wm.cxsr_allowed = false; + intel_set_memory_cxsr(dev_priv, false); + } } static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) @@ -11646,12 +11654,26 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, plane->base.id, was_visible, visible, turn_off, turn_on, mode_changed); - if (turn_on) + if (turn_on) { intel_crtc->atomic.update_wm_pre = true; - else if (turn_off) + /* must disable cxsr around plane enable/disable */ + if (plane->type != DRM_PLANE_TYPE_CURSOR) { + intel_crtc->atomic.disable_cxsr = true; + /* to potentially re-enable cxsr */ + intel_crtc->atomic.wait_vblank = true; + intel_crtc->atomic.update_wm_post = true; + } + } else if (turn_off) { intel_crtc->atomic.update_wm_post = true; - else if (intel_wm_need_update(plane, plane_state)) + /* must disable cxsr around plane enable/disable */ + if (plane->type != DRM_PLANE_TYPE_CURSOR) { + if (is_crtc_enabled) + intel_crtc->atomic.wait_vblank = true; + intel_crtc->atomic.disable_cxsr = true; + } + } else if (intel_wm_need_update(plane, plane_state)) { intel_crtc->atomic.update_wm_pre = true; + } if (visible) intel_crtc->atomic.fb_bits |= @@ -11808,8 +11830,8 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES) intel_crtc_check_initial_planes(crtc, crtc_state); - if (mode_changed) - intel_crtc->atomic.update_wm_post = !crtc_state->active; + if (mode_changed && !crtc_state->active) + intel_crtc->atomic.update_wm_post = true; if (mode_changed && crtc_state->enable && dev_priv->display.crtc_compute_clock && @@ -14089,6 +14111,8 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) intel_crtc->cursor_cntl = ~0; intel_crtc->cursor_size = ~0; + intel_crtc->wm.cxsr_allowed = true; + BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f26a680..4e8d13e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -507,6 +507,7 @@ struct intel_crtc_atomic_commit { /* Sleepable operations to perform before commit */ bool wait_for_flips; bool disable_fbc; + bool disable_cxsr; bool pre_disable_primary; bool update_wm_pre, update_wm_post; unsigned disabled_planes; @@ -565,6 +566,8 @@ struct intel_crtc { struct intel_pipe_wm active; /* SKL wm values currently in use */ struct skl_pipe_wm skl_active; + /* allow CxSR on this pipe */ + bool cxsr_allowed; } wm; int scanline_offset; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c7c90ce..b65817d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -335,6 +335,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) if (IS_VALLEYVIEW(dev)) { I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); POSTING_READ(FW_BLC_SELF_VLV); + dev_priv->wm.vlv.cxsr = enable; } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); POSTING_READ(FW_BLC_SELF); @@ -1116,7 +1117,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc) memset(wm_state, 0, sizeof(*wm_state)); - wm_state->cxsr = crtc->pipe != PIPE_C; + wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; if (IS_CHERRYVIEW(dev)) wm_state->num_levels = CHV_WM_NUM_LEVELS; else @@ -1369,10 +1370,8 @@ static void vlv_update_wm(struct drm_crtc *crtc) dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) chv_set_memory_pm5(dev_priv, false); - if (!wm.cxsr && dev_priv->wm.vlv.cxsr) { + if (!wm.cxsr && dev_priv->wm.vlv.cxsr) intel_set_memory_cxsr(dev_priv, false); - intel_wait_for_vblank(dev, pipe); - } /* FIXME should be part of crtc atomic commit */ vlv_pipe_set_fifo_size(intel_crtc); @@ -1385,10 +1384,8 @@ static void vlv_update_wm(struct drm_crtc *crtc) wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); - if (wm.cxsr && !dev_priv->wm.vlv.cxsr) { - intel_wait_for_vblank(dev, pipe); + if (wm.cxsr && !dev_priv->wm.vlv.cxsr) intel_set_memory_cxsr(dev_priv, true); - } if (wm.level >= VLV_WM_LEVEL_PM5 && dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)