[2/3] PCI: host: pcie-designware: add support for suspend and resume
diff mbox

Message ID 1435921425-15121-3-git-send-email-kishon@ti.com
State New
Headers show

Commit Message

Kishon Vijay Abraham I July 3, 2015, 11:03 a.m. UTC
Certain platforms require MSE bit to be cleared to set the master
in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
Controller Master Standby Behavior advises to use the clearing
of the local MSE bit to set the master in standby. Without this
some of the clocks do not idle).

Cleared the MSE bit on suspend and enabled it back on resume.
This is required to get suspend/resume working.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 drivers/pci/host/pcie-designware.c |   20 ++++++++++++++++++++
 drivers/pci/host/pcie-designware.h |    2 ++
 2 files changed, 22 insertions(+)

Comments

Pratyush Anand July 10, 2015, 1:22 p.m. UTC | #1
Hi Kishon,

On Fri, Jul 3, 2015 at 4:33 PM, Kishon Vijay Abraham I <kishon@ti.com> wrote:
> Certain platforms require MSE bit to be cleared to set the master
> in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
> Controller Master Standby Behavior advises to use the clearing
> of the local MSE bit to set the master in standby. Without this
> some of the clocks do not idle).
>
> Cleared the MSE bit on suspend and enabled it back on resume.
> This is required to get suspend/resume working.

Have you tested with a card having IO space memory as well.
I think you might need to require clear and enable PCI_COMMAND_IO
in suspend and resume respectively.

~Pratyush
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Kishon Vijay Abraham I July 10, 2015, 2:49 p.m. UTC | #2
Hi Pratyush,

On Friday 10 July 2015 06:52 PM, Pratyush Anand wrote:
> Hi Kishon,
> 
> On Fri, Jul 3, 2015 at 4:33 PM, Kishon Vijay Abraham I <kishon@ti.com> wrote:
>> Certain platforms require MSE bit to be cleared to set the master
>> in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
>> Controller Master Standby Behavior advises to use the clearing
>> of the local MSE bit to set the master in standby. Without this
>> some of the clocks do not idle).
>>
>> Cleared the MSE bit on suspend and enabled it back on resume.
>> This is required to get suspend/resume working.
> 
> Have you tested with a card having IO space memory as well.

I don't have any cards with IO space memory. Do you have any suggestion for
cards with IO space memory?
> I think you might need to require clear and enable PCI_COMMAND_IO
> in suspend and resume respectively.

okay.

Thanks
Kishon
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Pratyush Anand July 10, 2015, 3:30 p.m. UTC | #3
Hi Kishon,

On Fri, Jul 10, 2015 at 8:19 PM, Kishon Vijay Abraham I <kishon@ti.com> wrote:

[...]

>> Have you tested with a card having IO space memory as well.
>
> I don't have any cards with IO space memory. Do you have any suggestion for
> cards with IO space memory?

Sorry, I never used it either :(
IIRC, then Tim and Marek (in cc) had reported long back with some
issues of IO transaction
with SKY2 based card. They may let you know about exact card ID.

~Pratyush
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Marek Vasut July 10, 2015, 3:41 p.m. UTC | #4
On Friday, July 10, 2015 at 05:30:46 PM, Pratyush Anand wrote:
> Hi Kishon,

Hi,

> On Fri, Jul 10, 2015 at 8:19 PM, Kishon Vijay Abraham I <kishon@ti.com>
> wrote:
> 
> [...]
> 
> >> Have you tested with a card having IO space memory as well.
> > 
> > I don't have any cards with IO space memory. Do you have any suggestion
> > for cards with IO space memory?
> 
> Sorry, I never used it either :(
> IIRC, then Tim and Marek (in cc) had reported long back with some
> issues of IO transaction
> with SKY2 based card. They may let you know about exact card ID.

That was Tim, I didn't ever try with SKY2 , sorry.

Best regards,
Marek Vasut
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Jingoo Han July 12, 2015, 10:31 a.m. UTC | #5
On Friday, July 03, 2015 8:04 PM, Kishon Vijay Abraham I wrote:
> 
> Certain platforms require MSE bit to be cleared to set the master
> in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe

This patch is a work-around specific for DRA7xx chips?
If so, please move this patch to 'pci-dra7xx.c'.
I don't want to include chip-specific codes, because
'pcie-designware.c' is designed for including common codes.

Best regards,
Jingoo Han

> Controller Master Standby Behavior advises to use the clearing
> of the local MSE bit to set the master in standby. Without this
> some of the clocks do not idle).
> 
> Cleared the MSE bit on suspend and enabled it back on resume.
> This is required to get suspend/resume working.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
>  drivers/pci/host/pcie-designware.c |   20 ++++++++++++++++++++
>  drivers/pci/host/pcie-designware.h |    2 ++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 69486be..cfb2bd6 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -811,6 +811,26 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
>  }
> 
> +void dw_pcie_suspend_rc(struct pcie_port *pp)
> +{
> +	u32 val;
> +
> +	/* clear MSE */
> +	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
> +	val &= ~PCI_COMMAND_MEMORY;
> +	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
> +}
> +
> +void dw_pcie_resume_rc(struct pcie_port *pp)
> +{
> +	u32 val;
> +
> +	/* set MSE */
> +	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
> +	val |= PCI_COMMAND_MEMORY;
> +	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
> +}
> +
>  MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
>  MODULE_DESCRIPTION("Designware PCIe host controller driver");
>  MODULE_LICENSE("GPL v2");
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index d0bbd27..0df2dfa 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -83,5 +83,7 @@ void dw_pcie_msi_init(struct pcie_port *pp);
>  int dw_pcie_link_up(struct pcie_port *pp);
>  void dw_pcie_setup_rc(struct pcie_port *pp);
>  int dw_pcie_host_init(struct pcie_port *pp);
> +void dw_pcie_suspend_rc(struct pcie_port *pp);
> +void dw_pcie_resume_rc(struct pcie_port *pp);
> 
>  #endif /* _PCIE_DESIGNWARE_H */
> --
> 1.7.9.5

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Kishon Vijay Abraham I July 23, 2015, 12:50 p.m. UTC | #6
Hi,

On Sunday 12 July 2015 04:01 PM, Jingoo Han wrote:
> On Friday, July 03, 2015 8:04 PM, Kishon Vijay Abraham I wrote:
>>
>> Certain platforms require MSE bit to be cleared to set the master
>> in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
> 
> This patch is a work-around specific for DRA7xx chips?
> If so, please move this patch to 'pci-dra7xx.c'.
> I don't want to include chip-specific codes, because
> 'pcie-designware.c' is designed for including common codes.

Alright. Will change it that way in the next version.

Thanks
Kishon
> 
> Best regards,
> Jingoo Han
> 
>> Controller Master Standby Behavior advises to use the clearing
>> of the local MSE bit to set the master in standby. Without this
>> some of the clocks do not idle).
>>
>> Cleared the MSE bit on suspend and enabled it back on resume.
>> This is required to get suspend/resume working.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>> ---
>>  drivers/pci/host/pcie-designware.c |   20 ++++++++++++++++++++
>>  drivers/pci/host/pcie-designware.h |    2 ++
>>  2 files changed, 22 insertions(+)
>>
>> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
>> index 69486be..cfb2bd6 100644
>> --- a/drivers/pci/host/pcie-designware.c
>> +++ b/drivers/pci/host/pcie-designware.c
>> @@ -811,6 +811,26 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>>  	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
>>  }
>>
>> +void dw_pcie_suspend_rc(struct pcie_port *pp)
>> +{
>> +	u32 val;
>> +
>> +	/* clear MSE */
>> +	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
>> +	val &= ~PCI_COMMAND_MEMORY;
>> +	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
>> +}
>> +
>> +void dw_pcie_resume_rc(struct pcie_port *pp)
>> +{
>> +	u32 val;
>> +
>> +	/* set MSE */
>> +	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
>> +	val |= PCI_COMMAND_MEMORY;
>> +	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
>> +}
>> +
>>  MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
>>  MODULE_DESCRIPTION("Designware PCIe host controller driver");
>>  MODULE_LICENSE("GPL v2");
>> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
>> index d0bbd27..0df2dfa 100644
>> --- a/drivers/pci/host/pcie-designware.h
>> +++ b/drivers/pci/host/pcie-designware.h
>> @@ -83,5 +83,7 @@ void dw_pcie_msi_init(struct pcie_port *pp);
>>  int dw_pcie_link_up(struct pcie_port *pp);
>>  void dw_pcie_setup_rc(struct pcie_port *pp);
>>  int dw_pcie_host_init(struct pcie_port *pp);
>> +void dw_pcie_suspend_rc(struct pcie_port *pp);
>> +void dw_pcie_resume_rc(struct pcie_port *pp);
>>
>>  #endif /* _PCIE_DESIGNWARE_H */
>> --
>> 1.7.9.5
> 
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Patch
diff mbox

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 69486be..cfb2bd6 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -811,6 +811,26 @@  void dw_pcie_setup_rc(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
 }
 
+void dw_pcie_suspend_rc(struct pcie_port *pp)
+{
+	u32 val;
+
+	/* clear MSE */
+	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
+	val &= ~PCI_COMMAND_MEMORY;
+	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+}
+
+void dw_pcie_resume_rc(struct pcie_port *pp)
+{
+	u32 val;
+
+	/* set MSE */
+	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
+	val |= PCI_COMMAND_MEMORY;
+	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+}
+
 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
 MODULE_DESCRIPTION("Designware PCIe host controller driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index d0bbd27..0df2dfa 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -83,5 +83,7 @@  void dw_pcie_msi_init(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
+void dw_pcie_suspend_rc(struct pcie_port *pp);
+void dw_pcie_resume_rc(struct pcie_port *pp);
 
 #endif /* _PCIE_DESIGNWARE_H */