[2/7] drm/i915: Don't use link_bw for PLL setup

Message ID	1436184606-18729-3-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 6 Jul 2015 15:10:01 +0300 Message-Id: <1436184606-18729-3-git-send-email-ville.syrjala@linux.intel.com> In-Reply-To: <1436184606-18729-1-git-send-email-ville.syrjala@linux.intel.com> References: <1436184606-18729-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Don't use link_bw for PLL setup Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

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1436184606-18729-3-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)

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From: ville.syrjala@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Date: Mon,  6 Jul 2015 15:10:01 +0300
Message-Id: <1436184606-18729-3-git-send-email-ville.syrjala@linux.intel.com>
In-Reply-To: <1436184606-18729-1-git-send-email-ville.syrjala@linux.intel.com>
References: <1436184606-18729-1-git-send-email-ville.syrjala@linux.intel.com>
MIME-Version: 1.0
Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Don't use link_bw for PLL setup
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Commit Message

Ville Syrjälä July 6, 2015, 12:10 p.m. UTC

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use port_clock instead of link_bw when picking the PLL parameters for
DP. link_bw may be zero with an eDP 1.4 sink that supports
DP_LINK_RATE_SET so we shouln't use it for anything other than feed it
to the sink appropriately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 11 ++++------
 drivers/gpu/drm/i915/intel_dp.c  | 44 ++++++++++++++++++++--------------------
 2 files changed, 26 insertions(+), 29 deletions(-)

Comments

Sivakumar Thulasimani July 7, 2015, 8:05 a.m. UTC | #1

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>


On 7/6/2015 5:40 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use port_clock instead of link_bw when picking the PLL parameters for
> DP. link_bw may be zero with an eDP 1.4 sink that supports
> DP_LINK_RATE_SET so we shouln't use it for anything other than feed it
shouldn't ?
> to the sink appropriately.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ddi.c | 11 ++++------
>   drivers/gpu/drm/i915/intel_dp.c  | 44 ++++++++++++++++++++--------------------
>   2 files changed, 26 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9a40bfb..0d3cc98 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1574,17 +1574,14 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>   			 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
>   			 wrpll_params.central_freq;
>   	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
> -		struct drm_encoder *encoder = &intel_encoder->base;
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
> -		switch (intel_dp->link_bw) {
> -		case DP_LINK_BW_1_62:
> +		switch (crtc_state->port_clock / 2) {
> +		case 81000:
>   			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
>   			break;
> -		case DP_LINK_BW_2_7:
> +		case 135000:
>   			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
>   			break;
> -		case DP_LINK_BW_5_4:
> +		case 270000:
>   			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
>   			break;
>   		}
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index decefa1..3dd4342 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -48,28 +48,28 @@
>   #define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
>   
>   struct dp_link_dpll {
> -	int link_bw;
> +	int clock;
>   	struct dpll dpll;
>   };
>   
>   static const struct dp_link_dpll gen4_dpll[] = {
> -	{ DP_LINK_BW_1_62,
> +	{ 162000,
>   		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
> -	{ DP_LINK_BW_2_7,
> +	{ 270000,
>   		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
>   };
>   
>   static const struct dp_link_dpll pch_dpll[] = {
> -	{ DP_LINK_BW_1_62,
> +	{ 162000,
>   		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
> -	{ DP_LINK_BW_2_7,
> +	{ 270000,
>   		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
>   };
>   
>   static const struct dp_link_dpll vlv_dpll[] = {
> -	{ DP_LINK_BW_1_62,
> +	{ 162000,
>   		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
> -	{ DP_LINK_BW_2_7,
> +	{ 270000,
>   		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
>   };
>   
> @@ -83,11 +83,11 @@ static const struct dp_link_dpll chv_dpll[] = {
>   	 * m2 is stored in fixed point format using formula below
>   	 * (m2_int << 22) | m2_fraction
>   	 */
> -	{ DP_LINK_BW_1_62,	/* m2_int = 32, m2_fraction = 1677722 */
> +	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
>   		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
> -	{ DP_LINK_BW_2_7,	/* m2_int = 27, m2_fraction = 0 */
> +	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
>   		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
> -	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
> +	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
>   		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>   };
>   
> @@ -1099,7 +1099,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
>   }
>   
>   static void
> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
> +skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
>   {
>   	u32 ctrl1;
>   
> @@ -1111,7 +1111,7 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>   	pipe_config->dpll_hw_state.cfgcr2 = 0;
>   
>   	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
> -	switch (link_clock / 2) {
> +	switch (pipe_config->port_clock / 2) {
>   	case 81000:
>   		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
>   					      SKL_DPLL0);
> @@ -1145,19 +1145,19 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>   }
>   
>   static void
> -hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
> +hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
>   {
>   	memset(&pipe_config->dpll_hw_state, 0,
>   	       sizeof(pipe_config->dpll_hw_state));
>   
> -	switch (link_bw) {
> -	case DP_LINK_BW_1_62:
> +	switch (pipe_config->port_clock / 2) {
> +	case 81000:
>   		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
>   		break;
> -	case DP_LINK_BW_2_7:
> +	case 135000:
>   		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
>   		break;
> -	case DP_LINK_BW_5_4:
> +	case 270000:
>   		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
>   		break;
>   	}
> @@ -1204,7 +1204,7 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>   
>   static void
>   intel_dp_set_clock(struct intel_encoder *encoder,
> -		   struct intel_crtc_state *pipe_config, int link_bw)
> +		   struct intel_crtc_state *pipe_config)
>   {
>   	struct drm_device *dev = encoder->base.dev;
>   	const struct dp_link_dpll *divisor = NULL;
> @@ -1226,7 +1226,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>   
>   	if (divisor && count) {
>   		for (i = 0; i < count; i++) {
> -			if (link_bw == divisor[i].link_bw) {
> +			if (pipe_config->port_clock == divisor[i].clock) {
>   				pipe_config->dpll = divisor[i].dpll;
>   				pipe_config->clock_set = true;
>   				break;
> @@ -1498,13 +1498,13 @@ found:
>   	}
>   
>   	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
> -		skl_edp_set_pll_config(pipe_config, common_rates[clock]);
> +		skl_edp_set_pll_config(pipe_config);
>   	else if (IS_BROXTON(dev))
>   		/* handled in ddi */;
>   	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> -		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
> +		hsw_dp_set_ddi_pll_sel(pipe_config);
>   	else
> -		intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
> +		intel_dp_set_clock(encoder, pipe_config);
>   
>   	return true;
>   }

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9a40bfb..0d3cc98 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1574,17 +1574,14 @@  skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 			 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
 			 wrpll_params.central_freq;
 	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
-		struct drm_encoder *encoder = &intel_encoder->base;
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
+		switch (crtc_state->port_clock / 2) {
+		case 81000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
 			break;
-		case DP_LINK_BW_2_7:
+		case 135000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
 			break;
-		case DP_LINK_BW_5_4:
+		case 270000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
 			break;
 		}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index decefa1..3dd4342 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -48,28 +48,28 @@ 
 #define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
 
 struct dp_link_dpll {
-	int link_bw;
+	int clock;
 	struct dpll dpll;
 };
 
 static const struct dp_link_dpll gen4_dpll[] = {
-	{ DP_LINK_BW_1_62,
+	{ 162000,
 		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
-	{ DP_LINK_BW_2_7,
+	{ 270000,
 		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
 };
 
 static const struct dp_link_dpll pch_dpll[] = {
-	{ DP_LINK_BW_1_62,
+	{ 162000,
 		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
-	{ DP_LINK_BW_2_7,
+	{ 270000,
 		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 };
 
 static const struct dp_link_dpll vlv_dpll[] = {
-	{ DP_LINK_BW_1_62,
+	{ 162000,
 		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
-	{ DP_LINK_BW_2_7,
+	{ 270000,
 		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 };
 
@@ -83,11 +83,11 @@  static const struct dp_link_dpll chv_dpll[] = {
 	 * m2 is stored in fixed point format using formula below
 	 * (m2_int << 22) | m2_fraction
 	 */
-	{ DP_LINK_BW_1_62,	/* m2_int = 32, m2_fraction = 1677722 */
+	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
 		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
-	{ DP_LINK_BW_2_7,	/* m2_int = 27, m2_fraction = 0 */
+	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
 		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
-	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
+	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
@@ -1099,7 +1099,7 @@  intel_dp_connector_unregister(struct intel_connector *intel_connector)
 }
 
 static void
-skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
+skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
 {
 	u32 ctrl1;
 
@@ -1111,7 +1111,7 @@  skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
 	pipe_config->dpll_hw_state.cfgcr2 = 0;
 
 	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
-	switch (link_clock / 2) {
+	switch (pipe_config->port_clock / 2) {
 	case 81000:
 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 					      SKL_DPLL0);
@@ -1145,19 +1145,19 @@  skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
 }
 
 static void
-hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
+hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
 {
 	memset(&pipe_config->dpll_hw_state, 0,
 	       sizeof(pipe_config->dpll_hw_state));
 
-	switch (link_bw) {
-	case DP_LINK_BW_1_62:
+	switch (pipe_config->port_clock / 2) {
+	case 81000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 		break;
-	case DP_LINK_BW_2_7:
+	case 135000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 		break;
-	case DP_LINK_BW_5_4:
+	case 270000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 		break;
 	}
@@ -1204,7 +1204,7 @@  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 
 static void
 intel_dp_set_clock(struct intel_encoder *encoder,
-		   struct intel_crtc_state *pipe_config, int link_bw)
+		   struct intel_crtc_state *pipe_config)
 {
 	struct drm_device *dev = encoder->base.dev;
 	const struct dp_link_dpll *divisor = NULL;
@@ -1226,7 +1226,7 @@  intel_dp_set_clock(struct intel_encoder *encoder,
 
 	if (divisor && count) {
 		for (i = 0; i < count; i++) {
-			if (link_bw == divisor[i].link_bw) {
+			if (pipe_config->port_clock == divisor[i].clock) {
 				pipe_config->dpll = divisor[i].dpll;
 				pipe_config->clock_set = true;
 				break;
@@ -1498,13 +1498,13 @@  found:
 	}
 
 	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
-		skl_edp_set_pll_config(pipe_config, common_rates[clock]);
+		skl_edp_set_pll_config(pipe_config);
 	else if (IS_BROXTON(dev))
 		/* handled in ddi */;
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
+		hsw_dp_set_ddi_pll_sel(pipe_config);
 	else
-		intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
+		intel_dp_set_clock(encoder, pipe_config);
 
 	return true;
 }

[2/7] drm/i915: Don't use link_bw for PLL setup

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