From patchwork Thu Jul 9 09:17:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 6754341 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CAB1C9F2F0 for ; Thu, 9 Jul 2015 09:17:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EAD3520606 for ; Thu, 9 Jul 2015 09:17:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4FE69206F7 for ; Thu, 9 Jul 2015 09:17:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751255AbbGIJRg (ORCPT ); Thu, 9 Jul 2015 05:17:36 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:61317 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750998AbbGIJRb (ORCPT ); Thu, 9 Jul 2015 05:17:31 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id A38EAAEBCDE16; Thu, 9 Jul 2015 10:17:27 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 9 Jul 2015 10:17:29 +0100 Received: from jhogan-linux.le.imgtec.org (192.168.154.110) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Thu, 9 Jul 2015 10:17:29 +0100 From: James Hogan To: CC: James Hogan , Paolo Bonzini , Leon Alrae , Aurelien Jarno , Subject: [PATCH for 2.4 2/2] mips/kvm: Sync with newer MIPS KVM headers Date: Thu, 9 Jul 2015 10:17:15 +0100 Message-ID: <1436433435-24898-3-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 2.3.6 In-Reply-To: <1436433435-24898-1-git-send-email-james.hogan@imgtec.com> References: <1436433435-24898-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.154.110] Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The KVM_REG_MIPS_COUNT_* definitions are now included in linux-headers/asm-mips/kvm.h since commit b061808d39fa ("linux-headers: update linux headers to kvm/next"), therefore the duplicate definitions in target-mips/kvm.c can now be dropped (the definitions were tweaked slightly in commit 7a52ce8a1607 ("linux-headers: update") which triggered the following build warnings turned errors): target-mips/kvm.c:232:0: error: "KVM_REG_MIPS_COUNT_CTL" redefined [-Werror] linux-headers/asm/kvm.h:129:0: note: this is the location of the previous definition target-mips/kvm.c:236:0: error: "KVM_REG_MIPS_COUNT_RESUME" redefined [-Werror] linux-headers/asm/kvm.h:141:0: note: this is the location of the previous definition target-mips/kvm.c:239:0: error: "KVM_REG_MIPS_COUNT_HZ" redefined [-Werror] linux-headers/asm/kvm.h:147:0: note: this is the location of the previous definition Also update the MIPS_C0_{32,64} macros to utilise definitions more recently added to the asm-mips/kvm.h header. Signed-off-by: James Hogan Cc: Paolo Bonzini Cc: Leon Alrae Cc: Aurelien Jarno Cc: kvm@vger.kernel.org --- target-mips/kvm.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/target-mips/kvm.c b/target-mips/kvm.c index 7d2293d93492..bd64a70bcda0 100644 --- a/target-mips/kvm.c +++ b/target-mips/kvm.c @@ -212,10 +212,10 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) } #define MIPS_CP0_32(_R, _S) \ - (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S))) + (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) #define MIPS_CP0_64(_R, _S) \ - (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S))) + (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) @@ -232,17 +232,6 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) -/* CP0_Count control */ -#define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \ - 0x20000 | 0) -#define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001 /* master disable */ -/* CP0_Count resume monotonic nanoseconds */ -#define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \ - 0x20000 | 1) -/* CP0_Count rate in Hz */ -#define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \ - 0x20000 | 2) - static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, int32_t *addr) {