From patchwork Wed Jul 15 13:09:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kausal Malladi X-Patchwork-Id: 6798711 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C92B99F2F0 for ; Wed, 15 Jul 2015 13:10:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DF690205DB for ; Wed, 15 Jul 2015 13:10:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EC092205D1 for ; Wed, 15 Jul 2015 13:10:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CABC36E399; Wed, 15 Jul 2015 06:10:03 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 016D1720BB; Wed, 15 Jul 2015 06:10:01 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP; 15 Jul 2015 06:09:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,480,1432623600"; d="scan'208";a="606673324" Received: from kmalladi-desktop.iind.intel.com ([10.223.25.13]) by orsmga003.jf.intel.com with ESMTP; 15 Jul 2015 06:09:36 -0700 From: Kausal Malladi To: matthew.d.roper@intel.com, jesse.barnes@intel.com, damien.lespiau@intel.com, sonika.jindal@intel.com, durgadoss.r@intel.com, vijay.a.purushothaman@intel.com, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, hverkuil@xs4all.nl, daniel@fooishbar.org Subject: [PATCH 06/16] drm/i915: Load gamma color capabilities for CHV CRTC Date: Wed, 15 Jul 2015 18:39:30 +0530 Message-Id: <1436965780-6061-7-git-send-email-Kausal.Malladi@intel.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1436965780-6061-1-git-send-email-Kausal.Malladi@intel.com> References: <1436965780-6061-1-git-send-email-Kausal.Malladi@intel.com> Cc: annie.j.matheson@intel.com, avinash.reddy.palleti@intel.com, indranil.mukherjee@intel.com, dhanya.p.r@intel.com, sunil.kamath@intel.com, daniel.vetter@intel.com, susanta.bhattacharjee@intel.com, kiran.s.kumar@intel.com, shashank.sharma@intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As per Color Manager design, each driver is responsible to load its palette color correction and enhancement capabilities in the form of a DRM blob property, so that user space can query and read. This patch loads all CHV platform specific gamma color capabilities for CRTC into a blob that can be accessible by user space to query capabilities via DRM property interface. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/intel_color_manager.c | 48 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 4 +++ 2 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index baa4536..def20d0f 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,15 +27,63 @@ #include "intel_color_manager.h" +int get_chv_pipe_gamma_capabilities(struct drm_device *dev, + struct drm_palette_caps *palette_caps, struct drm_crtc *crtc) +{ + struct drm_property_blob *blob = NULL; + struct drm_mode_config *config = &dev->mode_config; + int ret; + + /* + * This function exposes best capability for DeGamma and Gamma + * For CHV, the DeGamma LUT has 65 entries + * and the best Gamma capability has 257 entries (CGM unit) + */ + palette_caps->version = CHV_PALETTE_STRUCT_VERSION; + palette_caps->num_samples_before_ctm = + CHV_DEGAMMA_MAX_VALS; + palette_caps->num_samples_after_ctm = + CHV_10BIT_GAMMA_MAX_VALS; + + ret = drm_property_replace_global_blob(dev, &blob, + sizeof(struct drm_palette_caps), + (const void *)palette_caps, + &crtc->base, config->prop_color_capabilities); + if (ret) { + DRM_ERROR("Error updating Gamma blob\n"); + return -EFAULT; + } + + return 0; +} + +int get_pipe_gamma_capabilities(struct drm_device *dev, + struct drm_palette_caps *palette_caps, struct drm_crtc *crtc) +{ + if (IS_CHERRYVIEW(dev)) + return get_chv_pipe_gamma_capabilities(dev, palette_caps, crtc); + return -EINVAL; +} + void intel_attach_color_properties_to_crtc(struct drm_device *dev, struct drm_mode_object *mode_obj) { struct drm_mode_config *config = &dev->mode_config; + struct drm_palette_caps *palette_caps; + struct drm_crtc *crtc; + int ret; if (IS_CHERRYVIEW(dev)) { + crtc = obj_to_crtc(mode_obj); if (config->prop_color_capabilities) drm_object_attach_property(mode_obj, config->prop_color_capabilities, 0); + palette_caps = kzalloc(sizeof(struct drm_palette_caps), + GFP_KERNEL); + ret = get_pipe_gamma_capabilities(dev, palette_caps, crtc); + if (ret) + DRM_ERROR("Error getting gamma capability for CHV\n"); + if (config->prop_palette_before_ctm) drm_object_attach_property(mode_obj, config->prop_palette_before_ctm, 0); diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 04c921d..51aeb91 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -27,3 +27,7 @@ #include #include #include "i915_drv.h" + +#define CHV_PALETTE_STRUCT_VERSION 1 +#define CHV_DEGAMMA_MAX_VALS 65 +#define CHV_10BIT_GAMMA_MAX_VALS 257