[v3,3/3] ARM: dts: dra7: Add scm_conf1 node and remove redundant nodes
diff mbox

Message ID 1437140844-6032-4-git-send-email-rogerq@ti.com
State New
Headers show

Commit Message

Roger Quadros July 17, 2015, 1:47 p.m. UTC
scm_conf1 maps the control register address space after the
padconf till the end.

Fix the scm_conf and pmx_core resource lengths. We need to add
4 bytes to include the last 32-bit register space.

Remove the redundant dra7_ctrl_core and dra7_ctrl_general nodes.
They are not used by anyone and no longer needed as they are
covered by scm_conf and scm_conf1.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

Comments

Tero Kristo July 20, 2015, 12:04 p.m. UTC | #1
On 07/17/2015 04:47 PM, Roger Quadros wrote:
> scm_conf1 maps the control register address space after the
> padconf till the end.
>
> Fix the scm_conf and pmx_core resource lengths. We need to add
> 4 bytes to include the last 32-bit register space.
>
> Remove the redundant dra7_ctrl_core and dra7_ctrl_general nodes.
> They are not used by anyone and no longer needed as they are
> covered by scm_conf and scm_conf1.

Looks like you are doing three things in this patch, maybe split it up 
as such?

>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>   arch/arm/boot/dts/dra7.dtsi | 19 ++++++++-----------
>   1 file changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 4a0718c..d07c34c 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -141,7 +141,7 @@
>   				dra7_pmx_core: pinmux@1400 {
>   					compatible = "ti,dra7-padconf",
>   						     "pinctrl-single";
> -					reg = <0x1400 0x0464>;
> +					reg = <0x1400 0x0468>;
>   					#address-cells = <1>;
>   					#size-cells = <0>;
>   					#interrupt-cells = <1>;
> @@ -149,6 +149,13 @@
>   					pinctrl-single,register-width = <32>;
>   					pinctrl-single,function-mask = <0x3fffffff>;
>   				};
> +
> +				scm_conf1: scm_conf@1 {

Should be ... scm_conf@1868?

Are there any users for this area anyway? I don't think we should map 
this area just for fun of it. Mostly it looks like this contains efuse 
values for OPPs, which should be mapped from the OPP layer, not as a 
generic syscon.

> +					compatible = "syscon";
> +					reg = <0x1868 0x03e0>;
> +					#address-cells = <1>;
> +					#size-cells = <1>;
> +				};
>   			};
>
>   			cm_core_aon: cm_core_aon@5000 {
> @@ -286,16 +293,6 @@
>   				#thermal-sensor-cells = <1>;
>   		};
>
> -		dra7_ctrl_core: ctrl_core@4a002000 {
> -			compatible = "syscon";
> -			reg = <0x4a002000 0x6d0>;
> -		};
> -
> -		dra7_ctrl_general: tisyscon@4a002e00 {
> -			compatible = "syscon";
> -			reg = <0x4a002e00 0x7c>;
> -		};

I thought I had removed these already and yes... this was done in commit 
d919501feffa8715147582c3ffce96fad0c7016f already, but seems they were 
added back in a resolution for a merge conflict later.

-Tero

> -
>   		sdma: dma-controller@4a056000 {
>   			compatible = "ti,omap4430-sdma";
>   			reg = <0x4a056000 0x1000>;
>

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Kishon Vijay Abraham I July 21, 2015, 5:11 a.m. UTC | #2
Hi,

On Monday 20 July 2015 05:34 PM, Tero Kristo wrote:
> On 07/17/2015 04:47 PM, Roger Quadros wrote:
>> scm_conf1 maps the control register address space after the
>> padconf till the end.
>>
>> Fix the scm_conf and pmx_core resource lengths. We need to add
>> 4 bytes to include the last 32-bit register space.
>>
>> Remove the redundant dra7_ctrl_core and dra7_ctrl_general nodes.
>> They are not used by anyone and no longer needed as they are
>> covered by scm_conf and scm_conf1.
> 
> Looks like you are doing three things in this patch, maybe split it up 
> as such?
> 
>>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>>   arch/arm/boot/dts/dra7.dtsi | 19 ++++++++-----------
>>   1 file changed, 8 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 4a0718c..d07c34c 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -141,7 +141,7 @@
>>   				dra7_pmx_core: pinmux@1400 {
>>   					compatible = "ti,dra7-padconf",
>>   						     "pinctrl-single";
>> -					reg = <0x1400 0x0464>;
>> +					reg = <0x1400 0x0468>;
>>   					#address-cells = <1>;
>>   					#size-cells = <0>;
>>   					#interrupt-cells = <1>;
>> @@ -149,6 +149,13 @@
>>   					pinctrl-single,register-width = <32>;
>>   					pinctrl-single,function-mask = <0x3fffffff>;
>>   				};
>> +
>> +				scm_conf1: scm_conf@1 {
> 
> Should be ... scm_conf@1868?
> 
> Are there any users for this area anyway? I don't think we should map 
> this area just for fun of it. Mostly it looks like this contains efuse 
> values for OPPs, which should be mapped from the OPP layer, not as a 
> generic syscon.

The last few registers are used for PCIe PHY and I'll be needing it for the
next version of my patch series.

Thanks
Kishon
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Roger Quadros July 27, 2015, 9:40 a.m. UTC | #3
On 20/07/15 15:04, Tero Kristo wrote:
> On 07/17/2015 04:47 PM, Roger Quadros wrote:
>> scm_conf1 maps the control register address space after the
>> padconf till the end.
>>
>> Fix the scm_conf and pmx_core resource lengths. We need to add
>> 4 bytes to include the last 32-bit register space.
>>
>> Remove the redundant dra7_ctrl_core and dra7_ctrl_general nodes.
>> They are not used by anyone and no longer needed as they are
>> covered by scm_conf and scm_conf1.
> 
> Looks like you are doing three things in this patch, maybe split it up as such?

OK.

> 
>>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>>   arch/arm/boot/dts/dra7.dtsi | 19 ++++++++-----------
>>   1 file changed, 8 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 4a0718c..d07c34c 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -141,7 +141,7 @@
>>                   dra7_pmx_core: pinmux@1400 {
>>                       compatible = "ti,dra7-padconf",
>>                                "pinctrl-single";
>> -                    reg = <0x1400 0x0464>;
>> +                    reg = <0x1400 0x0468>;
>>                       #address-cells = <1>;
>>                       #size-cells = <0>;
>>                       #interrupt-cells = <1>;
>> @@ -149,6 +149,13 @@
>>                       pinctrl-single,register-width = <32>;
>>                       pinctrl-single,function-mask = <0x3fffffff>;
>>                   };
>> +
>> +                scm_conf1: scm_conf@1 {
> 
> Should be ... scm_conf@1868?

OK.

> 
> Are there any users for this area anyway? I don't think we should map this area just for fun of it. Mostly it looks like this contains efuse values for OPPs, which should be mapped from the OPP layer, not as a generic syscon.

OK then, I'll only include the CTRL_CORE_SMA_SW_2..9 registers in this region.


cheers,
-roger

> 
>> +                    compatible = "syscon";
>> +                    reg = <0x1868 0x03e0>;
>> +                    #address-cells = <1>;
>> +                    #size-cells = <1>;
>> +                };
>>               };
>>
>>               cm_core_aon: cm_core_aon@5000 {
>> @@ -286,16 +293,6 @@
>>                   #thermal-sensor-cells = <1>;
>>           };
>>
>> -        dra7_ctrl_core: ctrl_core@4a002000 {
>> -            compatible = "syscon";
>> -            reg = <0x4a002000 0x6d0>;
>> -        };
>> -
>> -        dra7_ctrl_general: tisyscon@4a002e00 {
>> -            compatible = "syscon";
>> -            reg = <0x4a002e00 0x7c>;
>> -        };
> 
> I thought I had removed these already and yes... this was done in commit d919501feffa8715147582c3ffce96fad0c7016f already, but seems they were added back in a resolution for a merge conflict later.
> 
> -Tero
> 
>> -
>>           sdma: dma-controller@4a056000 {
>>               compatible = "ti,omap4430-sdma";
>>               reg = <0x4a056000 0x1000>;
>>
> 
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Roger Quadros July 27, 2015, 9:40 a.m. UTC | #4
On 21/07/15 08:11, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Monday 20 July 2015 05:34 PM, Tero Kristo wrote:
>> On 07/17/2015 04:47 PM, Roger Quadros wrote:
>>> scm_conf1 maps the control register address space after the
>>> padconf till the end.
>>>
>>> Fix the scm_conf and pmx_core resource lengths. We need to add
>>> 4 bytes to include the last 32-bit register space.
>>>
>>> Remove the redundant dra7_ctrl_core and dra7_ctrl_general nodes.
>>> They are not used by anyone and no longer needed as they are
>>> covered by scm_conf and scm_conf1.
>>
>> Looks like you are doing three things in this patch, maybe split it up 
>> as such?
>>
>>>
>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>>> ---
>>>   arch/arm/boot/dts/dra7.dtsi | 19 ++++++++-----------
>>>   1 file changed, 8 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>>> index 4a0718c..d07c34c 100644
>>> --- a/arch/arm/boot/dts/dra7.dtsi
>>> +++ b/arch/arm/boot/dts/dra7.dtsi
>>> @@ -141,7 +141,7 @@
>>>   				dra7_pmx_core: pinmux@1400 {
>>>   					compatible = "ti,dra7-padconf",
>>>   						     "pinctrl-single";
>>> -					reg = <0x1400 0x0464>;
>>> +					reg = <0x1400 0x0468>;
>>>   					#address-cells = <1>;
>>>   					#size-cells = <0>;
>>>   					#interrupt-cells = <1>;
>>> @@ -149,6 +149,13 @@
>>>   					pinctrl-single,register-width = <32>;
>>>   					pinctrl-single,function-mask = <0x3fffffff>;
>>>   				};
>>> +
>>> +				scm_conf1: scm_conf@1 {
>>
>> Should be ... scm_conf@1868?
>>
>> Are there any users for this area anyway? I don't think we should map 
>> this area just for fun of it. Mostly it looks like this contains efuse 
>> values for OPPs, which should be mapped from the OPP layer, not as a 
>> generic syscon.
> 
> The last few registers are used for PCIe PHY and I'll be needing it for the
> next version of my patch series.

OK noted. Will exclude the PCIe registers from this region.

cheers,
-roger
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Patch
diff mbox

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 4a0718c..d07c34c 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -141,7 +141,7 @@ 
 				dra7_pmx_core: pinmux@1400 {
 					compatible = "ti,dra7-padconf",
 						     "pinctrl-single";
-					reg = <0x1400 0x0464>;
+					reg = <0x1400 0x0468>;
 					#address-cells = <1>;
 					#size-cells = <0>;
 					#interrupt-cells = <1>;
@@ -149,6 +149,13 @@ 
 					pinctrl-single,register-width = <32>;
 					pinctrl-single,function-mask = <0x3fffffff>;
 				};
+
+				scm_conf1: scm_conf@1 {
+					compatible = "syscon";
+					reg = <0x1868 0x03e0>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+				};
 			};
 
 			cm_core_aon: cm_core_aon@5000 {
@@ -286,16 +293,6 @@ 
 				#thermal-sensor-cells = <1>;
 		};
 
-		dra7_ctrl_core: ctrl_core@4a002000 {
-			compatible = "syscon";
-			reg = <0x4a002000 0x6d0>;
-		};
-
-		dra7_ctrl_general: tisyscon@4a002e00 {
-			compatible = "syscon";
-			reg = <0x4a002e00 0x7c>;
-		};
-
 		sdma: dma-controller@4a056000 {
 			compatible = "ti,omap4430-sdma";
 			reg = <0x4a056000 0x1000>;