From patchwork Mon Jul 20 22:33:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 6831181 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E3B50C05AC for ; Mon, 20 Jul 2015 22:34:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3382D205BE for ; Mon, 20 Jul 2015 22:34:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 32BB5205CB for ; Mon, 20 Jul 2015 22:34:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756836AbbGTWeK (ORCPT ); Mon, 20 Jul 2015 18:34:10 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:44818 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755574AbbGTWd7 (ORCPT ); Mon, 20 Jul 2015 18:33:59 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id t6KMXqtb024863; Mon, 20 Jul 2015 17:33:52 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t6KMXqci014614; Mon, 20 Jul 2015 17:33:52 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Mon, 20 Jul 2015 17:33:20 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t6KMXpLF030236; Mon, 20 Jul 2015 17:33:51 -0500 Received: from localhost (irmo.am.dhcp.ti.com [128.247.9.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id t6KMXp925723; Mon, 20 Jul 2015 17:33:51 -0500 (CDT) From: Suman Anna To: Joerg Roedel CC: , Laurent Pinchart , , Suman Anna Subject: [PATCH 08/11] iommu/omap: Use BIT(x) macros in omap-iopgtable.h Date: Mon, 20 Jul 2015 17:33:30 -0500 Message-ID: <1437431613-55656-9-git-send-email-s-anna@ti.com> X-Mailer: git-send-email 2.4.4 In-Reply-To: <1437431613-55656-1-git-send-email-s-anna@ti.com> References: <1437431613-55656-1-git-send-email-s-anna@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Switch to using the BIT(x) macros in omap-iopgtable.h where possible. This eliminates the following checkpatch check warning: "CHECK: Prefer using the BIT macro" A couple of macros that used zero bit shifting are defined directly to avoid the above warning on one of the macros. Signed-off-by: Suman Anna --- drivers/iommu/omap-iopgtable.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/omap-iopgtable.h b/drivers/iommu/omap-iopgtable.h index bfde5405f514..01a315227bf0 100644 --- a/drivers/iommu/omap-iopgtable.h +++ b/drivers/iommu/omap-iopgtable.h @@ -13,25 +13,27 @@ #ifndef _OMAP_IOPGTABLE_H #define _OMAP_IOPGTABLE_H +#include + /* * "L2 table" address mask and size definitions. */ #define IOPGD_SHIFT 20 -#define IOPGD_SIZE (1UL << IOPGD_SHIFT) +#define IOPGD_SIZE BIT(IOPGD_SHIFT) #define IOPGD_MASK (~(IOPGD_SIZE - 1)) /* * "section" address mask and size definitions. */ #define IOSECTION_SHIFT 20 -#define IOSECTION_SIZE (1UL << IOSECTION_SHIFT) +#define IOSECTION_SIZE BIT(IOSECTION_SHIFT) #define IOSECTION_MASK (~(IOSECTION_SIZE - 1)) /* * "supersection" address mask and size definitions. */ #define IOSUPER_SHIFT 24 -#define IOSUPER_SIZE (1UL << IOSUPER_SHIFT) +#define IOSUPER_SIZE BIT(IOSUPER_SHIFT) #define IOSUPER_MASK (~(IOSUPER_SIZE - 1)) #define PTRS_PER_IOPGD (1UL << (32 - IOPGD_SHIFT)) @@ -41,14 +43,14 @@ * "small page" address mask and size definitions. */ #define IOPTE_SHIFT 12 -#define IOPTE_SIZE (1UL << IOPTE_SHIFT) +#define IOPTE_SIZE BIT(IOPTE_SHIFT) #define IOPTE_MASK (~(IOPTE_SIZE - 1)) /* * "large page" address mask and size definitions. */ #define IOLARGE_SHIFT 16 -#define IOLARGE_SIZE (1UL << IOLARGE_SHIFT) +#define IOLARGE_SIZE BIT(IOLARGE_SHIFT) #define IOLARGE_MASK (~(IOLARGE_SIZE - 1)) #define PTRS_PER_IOPTE (1UL << (IOPGD_SHIFT - IOPTE_SHIFT)) @@ -72,16 +74,16 @@ static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask) /* * some descriptor attributes. */ -#define IOPGD_TABLE (1 << 0) -#define IOPGD_SECTION (2 << 0) -#define IOPGD_SUPER (1 << 18 | 2 << 0) +#define IOPGD_TABLE (1) +#define IOPGD_SECTION (2) +#define IOPGD_SUPER (BIT(18) | IOPGD_SECTION) #define iopgd_is_table(x) (((x) & 3) == IOPGD_TABLE) #define iopgd_is_section(x) (((x) & (1 << 18 | 3)) == IOPGD_SECTION) #define iopgd_is_super(x) (((x) & (1 << 18 | 3)) == IOPGD_SUPER) -#define IOPTE_SMALL (2 << 0) -#define IOPTE_LARGE (1 << 0) +#define IOPTE_SMALL (2) +#define IOPTE_LARGE (1) #define iopte_is_small(x) (((x) & 2) == IOPTE_SMALL) #define iopte_is_large(x) (((x) & 3) == IOPTE_LARGE)