[v2,1/2] ARM: rockchip: set correct stabilization thresholds in suspend
diff mbox

Message ID 4610448.RXXf22Qoxl@diego
State New
Headers show

Commit Message

Heiko Stuebner July 23, 2015, 8:29 a.m. UTC
Currently the stabilization thresholds for the oscillator and external pmu
are statically set to 30ms based on a 32kHz clock rate. This leaves out the
case when we don't switch to the 32kHz clock when only entering the shallow
suspend mode where the logic keeps running.

So, set the correct threshold after we have determined if we switch to the
32kHz clock or stay with the 24MHz one.

Reported-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
changes since v1:
- 24MHz oriented threshold is only needed in shallow suspend, the deep
  suspend always switches to 32kHz and only leaves the 24MHz oscillator
  running if needed for stuff like usb wakeup

 arch/arm/mach-rockchip/pm.c | 11 ++++++++---
 arch/arm/mach-rockchip/pm.h |  4 ----
 2 files changed, 8 insertions(+), 7 deletions(-)

Comments

Heiko Stuebner July 24, 2015, 11:09 p.m. UTC | #1
Hi Chris,

Am Donnerstag, 23. Juli 2015, 10:29:34 schrieb Heiko Stübner:
> diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
> index 892bace..04d3028 100644
> --- a/arch/arm/mach-rockchip/pm.c
> +++ b/arch/arm/mach-rockchip/pm.c
> @@ -145,6 +145,10 @@ static void rk3288_slp_mode_set(int level)
> 
>  		mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
>  			     BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
> +
> +		/* 30ms on a 32kHz clock for osc and pmic stabilization */
> +		regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 32 * 30);
> +		regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);

The deep suspend mode has two bits handling the 32kHz clock switch (PMU_USE_LF 
and ALIVE_USE_LF). Just for my understanding, are these always supposed to be 
set to the same value or can there be a case when only one of them is set?

Also when deciding the correct stabilization delays on which of the two are 
these dependant?

I.e. something like

  stabl_cnt = PMU_PMU_USE_LF ? 32 : 24000
  osc_cnt = PMU_ALIVE_USE_LF ? 32 : 24000

or are these always to be set similarly?


Thanks
Heiko
Chris Zhong July 31, 2015, 2:57 a.m. UTC | #2
Hi Heiko

On 07/25/2015 07:09 AM, Heiko Stübner wrote:
> Hi Chris,
>
> Am Donnerstag, 23. Juli 2015, 10:29:34 schrieb Heiko Stübner:
>> diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
>> index 892bace..04d3028 100644
>> --- a/arch/arm/mach-rockchip/pm.c
>> +++ b/arch/arm/mach-rockchip/pm.c
>> @@ -145,6 +145,10 @@ static void rk3288_slp_mode_set(int level)
>>
>>   		mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
>>   			     BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
>> +
>> +		/* 30ms on a 32kHz clock for osc and pmic stabilization */
>> +		regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 32 * 30);
>> +		regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);
> The deep suspend mode has two bits handling the 32kHz clock switch (PMU_USE_LF
> and ALIVE_USE_LF). Just for my understanding, are these always supposed to be
> set to the same value or can there be a case when only one of them is set?
If we want to close the 24Mhz osc, these 2 bit must to be set 1;
if 24Mhz still working, we can disable any one of these 2 bit, or 
disable both of them .

> Also when deciding the correct stabilization delays on which of the two are
> these dependant?
>
> I.e. something like
>
>    stabl_cnt = PMU_PMU_USE_LF ? 32 : 24000
>    osc_cnt = PMU_ALIVE_USE_LF ? 32 : 24000
>
> or are these always to be set similarly?

stabl_cnt is the time of waiting PMIC(RK808) to be stable, so if we hold the GLOBAL_PWROFF pin low,
we do not need wait this time, stabl_cnt = 0 is good in this case.
  
osc_cnt is the time of waiting 24Mhz osc to be stable, so if the 24Mhz osc is still working during suspend,
this time could be set to 0.

And these 2 time count is base on PMU_PMU_USE_LF:
stabl_cnt = PMU_PMU_USE_LF ? 32 : 24000
osc_cnt = PMU_PMU_USE_LF ? 32 : 24000

>
>
> Thanks
> Heiko
>
>
>

Patch
diff mbox

diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index 892bace..04d3028 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -145,6 +145,10 @@  static void rk3288_slp_mode_set(int level)
 
 		mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
 			     BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
+
+		/* 30ms on a 32kHz clock for osc and pmic stabilization */
+		regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 32 * 30);
+		regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);
 	} else {
 		/*
 		 * arm off, logic normal
@@ -152,6 +156,10 @@  static void rk3288_slp_mode_set(int level)
 		 * wakeup will be error
 		 */
 		mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
+
+		/* 30ms on a 24MHz clock for osc and pmic stabilization */
+		regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 24000 * 30);
+		regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30);
 	}
 
 	regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
@@ -262,9 +270,6 @@  static int rk3288_suspend_init(struct device_node *np)
 	memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
 	       rk3288_bootram_sz);
 
-	regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);
-	regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);
-
 	return 0;
 }
 
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
index b6494c2..8a55ee2 100644
--- a/arch/arm/mach-rockchip/pm.h
+++ b/arch/arm/mach-rockchip/pm.h
@@ -62,10 +62,6 @@  static inline void rockchip_suspend_init(void)
 /* PMU_WAKEUP_CFG1 bits */
 #define PMU_ARMINT_WAKEUP_EN		BIT(0)
 
-/* wait 30ms for OSC stable and 30ms for pmic stable */
-#define OSC_STABL_CNT_THRESH	(32 * 30)
-#define PMU_STABL_CNT_THRESH	(32 * 30)
-
 enum rk3288_pwr_mode_con {
 	PMU_PWR_MODE_EN = 0,
 	PMU_CLK_CORE_SRC_GATE_EN,