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[212.51.149.109]) by smtp.gmail.com with ESMTPSA id fa8sm4089922wib.14.2015.07.24.08.37.38 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Jul 2015 08:37:39 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Fri, 24 Jul 2015 17:40:12 +0200 Message-Id: <1437752415-8624-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1437738912-15971-3-git-send-email-daniel.vetter@ffwll.ch> References: <1437738912-15971-3-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter , Daniel Vetter Subject: [Intel-gfx] [PATCH 1/4] drm/i915: kerneldoc for fences X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP v2: Clarify that this is about fence _registers_. Also clarify that the fence code revokes cpu ptes and not gtt ptes. Both suggested by Chris. Cc: Chris Wilson Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson --- Documentation/DocBook/drm.tmpl | 5 +++ drivers/gpu/drm/i915/i915_gem_fence.c | 75 +++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 86680f074111..d7dc91b7e98c 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -4051,6 +4051,11 @@ int num_ioctls; !Idrivers/gpu/drm/i915/i915_gem_gtt.c + Global GTT Fence Handling +!Pdrivers/gpu/drm/i915/i915_gem_fence.c fence register handling +!Idrivers/gpu/drm/i915/i915_gem_fence.c + + Buffer Object Eviction This section documents the interface functions for evicting buffer diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c index d3284ee04794..0434c42d8c11 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence.c +++ b/drivers/gpu/drm/i915/i915_gem_fence.c @@ -25,6 +25,36 @@ #include #include "i915_drv.h" +/** + * DOC: fence register handling + * + * Important to avoid confusions: "fences" in the i915 driver are not execution + * fences used to track command completion but hardware detiler objects which + * wrap a given range of the global GTT. Each platform has only a fairly limited + * set of these objects. + * + * Fences are used to detile GTT memory mappings. They're also connected to the + * hardware frontbuffer render tracking and hence interract with frontbuffer + * conmpression. Furthermore on older platforms fences are required for tiled + * objects used by the display engine. They can also be used by the render + * engine - they're required for blitter commands and are optional for render + * commands. But on gen4+ both display (with the exception of fbc) and rendering + * have their own tiling state bits and don't need fences. + * + * Also note that fences only support X and Y tiling and hence can't be used for + * the fancier new tiling formats like W, Ys and Yf. + * + * Finally note that because fences are such a restricted resource they're + * dynamically associated with objects. Furthermore fence state is committed to + * the hardware lazily to avoid unecessary stalls on gen2/3. Therefore code must + * explictly call i915_gem_object_get_fence() to synchronize fencing status + * for cpu access. Also note that some code wants an unfenced view, for those + * cases the fence can be removed forcefully with i915_gem_object_put_fence(). + * + * Internally these functions will synchronize with userspace access by removing + * CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed. + */ + static void i965_write_fence_reg(struct drm_device *dev, int reg, struct drm_i915_gem_object *obj) { @@ -247,6 +277,17 @@ i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) return 0; } +/** + * i915_gem_object_put_fence - force-remove fence for an object + * @obj: object to map through a fence reg + * + * This function force-removes any fence from the given object, which is useful + * if the kernel wants to do untiled GTT access. + * + * Returns: + * + * 0 on success, negative error code on failure. + */ int i915_gem_object_put_fence(struct drm_i915_gem_object *obj) { @@ -322,6 +363,10 @@ deadlock: * and tiling format. * * For an untiled surface, this removes any existing fence. + * + * Returns: + * + * 0 on success, negative error code on failure. */ int i915_gem_object_get_fence(struct drm_i915_gem_object *obj) @@ -374,6 +419,21 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj) return 0; } +/** + * i915_gem_object_pin_fence - pin fencing state + * @obj: object to pin fencing for + * + * This pins the fencing state (whether tiled or untiled) to make sure the + * object is ready to be used as a scanout target. Fencing status must be + * synchronize first by calling i915_gem_object_get_fence(): + * + * The resulting fence pin reference must be released again with + * i915_gem_object_unpin_fence(). + * + * Returns: + * + * True if the object has a fence, false otherwise. + */ bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) { @@ -390,6 +450,14 @@ i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) return false; } +/** + * i915_gem_object_unpin_fence - unpin fencing state + * @obj: object to unpin fencing for + * + * This releases the fence pin reference acquired through + * i915_gem_object_pin_fence. It will handle both objects with and without an + * attached fence correctly, callers do not need to distinguish this. + */ void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) { @@ -400,6 +468,13 @@ i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) } } +/** + * i915_gem_restore_fences - restore fence state + * @dev: DRM device + * + * Restore the hw fence state to match the software tracking again, to be called + * after a gpu reset and on resume. + */ void i915_gem_restore_fences(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private;