| Message ID | 1437850839-16782-18-git-send-email-animesh.manna@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sunday 26 July 2015 12:30 AM, Animesh Manna wrote: > As csr firmware is taking care of loading the firmware, > so no need for driver to load again. > > Cc: Damien Lespiau <damien.lespiau@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Sunil Kamath <sunil.kamath@intel.com> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 77b35fd..f5e720b 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1048,7 +1048,6 @@ static int skl_resume_prepare(struct drm_i915_private *dev_priv) > skl_disable_dc6(dev_priv); > > skl_init_cdclk(dev_priv); > - intel_csr_load_program(dev_priv); The context save and restore program is reset on cold boot, warm reset, PCI function level reset, and hibernate/suspend. Will it not impact? - Sunil > > return 0; > }
On Tuesday 28 July 2015 04:53 PM, Sunil Kamath wrote: > On Sunday 26 July 2015 12:30 AM, Animesh Manna wrote: >> As csr firmware is taking care of loading the firmware, >> so no need for driver to load again. >> >> Cc: Damien Lespiau <damien.lespiau@intel.com> >> Cc: Imre Deak <imre.deak@intel.com> >> Cc: Sunil Kamath <sunil.kamath@intel.com> >> Signed-off-by: Animesh Manna <animesh.manna@intel.com> >> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.c | 1 - >> 1 file changed, 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c >> b/drivers/gpu/drm/i915/i915_drv.c >> index 77b35fd..f5e720b 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -1048,7 +1048,6 @@ static int skl_resume_prepare(struct >> drm_i915_private *dev_priv) >> skl_disable_dc6(dev_priv); >> skl_init_cdclk(dev_priv); >> - intel_csr_load_program(dev_priv); > > The context save and restore program is reset on cold boot, warm > reset, PCI function level reset, and hibernate/suspend. > > Will it not impact? > > - Sunil If the concern is about checking DC5/DC6 counters, isn't it good idea to add that as debug print before f/w reload? Than to avoid completely reloading of entire firmware? - Sunil >> return 0; >> } >
On Tuesday 28 July 2015 04:53 PM, Sunil Kamath wrote: > On Sunday 26 July 2015 12:30 AM, Animesh Manna wrote: >> As csr firmware is taking care of loading the firmware, >> so no need for driver to load again. >> >> Cc: Damien Lespiau <damien.lespiau@intel.com> >> Cc: Imre Deak <imre.deak@intel.com> >> Cc: Sunil Kamath <sunil.kamath@intel.com> >> Signed-off-by: Animesh Manna <animesh.manna@intel.com> >> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.c | 1 - >> 1 file changed, 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c >> b/drivers/gpu/drm/i915/i915_drv.c >> index 77b35fd..f5e720b 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -1048,7 +1048,6 @@ static int skl_resume_prepare(struct >> drm_i915_private *dev_priv) >> skl_disable_dc6(dev_priv); >> skl_init_cdclk(dev_priv); >> - intel_csr_load_program(dev_priv); > > The context save and restore program is reset on cold boot, warm > reset, PCI function level reset, and hibernate/suspend. > > Will it not impact? > > - Sunil If the intention is just to check the DC5/DC6 counters, why cant we just add debug prints before f/w reload? Than to just avoiding reloading fw itself. - Sunil >> return 0; >> } >
On Wednesday 29 July 2015 04:40 PM, Sunil Kamath wrote: > On Tuesday 28 July 2015 04:53 PM, Sunil Kamath wrote: >> On Sunday 26 July 2015 12:30 AM, Animesh Manna wrote: >>> As csr firmware is taking care of loading the firmware, >>> so no need for driver to load again. >>> >>> Cc: Damien Lespiau <damien.lespiau@intel.com> >>> Cc: Imre Deak <imre.deak@intel.com> >>> Cc: Sunil Kamath <sunil.kamath@intel.com> >>> Signed-off-by: Animesh Manna <animesh.manna@intel.com> >>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> >>> --- >>> drivers/gpu/drm/i915/i915_drv.c | 1 - >>> 1 file changed, 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_drv.c >>> b/drivers/gpu/drm/i915/i915_drv.c >>> index 77b35fd..f5e720b 100644 >>> --- a/drivers/gpu/drm/i915/i915_drv.c >>> +++ b/drivers/gpu/drm/i915/i915_drv.c >>> @@ -1048,7 +1048,6 @@ static int skl_resume_prepare(struct >>> drm_i915_private *dev_priv) >>> skl_disable_dc6(dev_priv); >>> skl_init_cdclk(dev_priv); >>> - intel_csr_load_program(dev_priv); >> >> The context save and restore program is reset on cold boot, warm >> reset, PCI function level reset, and hibernate/suspend. >> >> Will it not impact? >> >> - Sunil > > If the intention is just to check the DC5/DC6 counters, why cant we > just add debug prints before f/w reload? Than to just avoiding > reloading fw itself. > > - Sunil Dont hurry on this patch. Need to close on the above opens. - Sunil >>> return 0; >>> } >> >
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 77b35fd..f5e720b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1048,7 +1048,6 @@ static int skl_resume_prepare(struct drm_i915_private *dev_priv) skl_disable_dc6(dev_priv); skl_init_cdclk(dev_priv); - intel_csr_load_program(dev_priv); return 0; }