| Message ID | 1437899840-32153-13-git-send-email-uma.shankar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sun, 26 Jul 2015, Uma Shankar <uma.shankar@intel.com> wrote: > DSP CLK_GATE registers are specific to BYT and CHT. > Avoid programming the same for BXT platform. > > v2: Rebased on latest drm nightly branch. > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index 350e10a..d0b26c8 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -612,6 +612,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) > > static void intel_dsi_post_disable(struct intel_encoder *encoder) > { > + struct drm_device *dev = encoder->base.dev; > struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > u32 val; > @@ -622,9 +623,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder) > > intel_dsi_clear_device_ready(encoder); > > - val = I915_READ(DSPCLK_GATE_D); > - val &= ~DPOUNIT_CLOCK_GATE_DISABLE; > - I915_WRITE(DSPCLK_GATE_D, val); > + if (!IS_BROXTON(dev)) { You can use dev_priv for IS_BROXTON. > + val = I915_READ(DSPCLK_GATE_D); > + val &= ~DPOUNIT_CLOCK_GATE_DISABLE; > + I915_WRITE(DSPCLK_GATE_D, val); > + } > > drm_panel_unprepare(intel_dsi->panel); > > -- > 1.7.9.5 >
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 350e10a..d0b26c8 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -612,6 +612,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) static void intel_dsi_post_disable(struct intel_encoder *encoder) { + struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); u32 val; @@ -622,9 +623,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder) intel_dsi_clear_device_ready(encoder); - val = I915_READ(DSPCLK_GATE_D); - val &= ~DPOUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, val); + if (!IS_BROXTON(dev)) { + val = I915_READ(DSPCLK_GATE_D); + val &= ~DPOUNIT_CLOCK_GATE_DISABLE; + I915_WRITE(DSPCLK_GATE_D, val); + } drm_panel_unprepare(intel_dsi->panel);
DSP CLK_GATE registers are specific to BYT and CHT. Avoid programming the same for BXT platform. v2: Rebased on latest drm nightly branch. Signed-off-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/intel_dsi.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)