From patchwork Mon Jul 27 06:24:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 6869191 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9546B9F358 for ; Mon, 27 Jul 2015 06:26:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A7FBC2062B for ; Mon, 27 Jul 2015 06:26:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 95E7A2062F for ; Mon, 27 Jul 2015 06:26:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751388AbbG0GZP (ORCPT ); Mon, 27 Jul 2015 02:25:15 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:49820 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751362AbbG0GZK (ORCPT ); Mon, 27 Jul 2015 02:25:10 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t6R6P7Wl015799; Mon, 27 Jul 2015 01:25:07 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t6R6P7xf018815; Mon, 27 Jul 2015 01:25:07 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Mon, 27 Jul 2015 01:25:06 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t6R6OvJI009570; Mon, 27 Jul 2015 01:25:04 -0500 From: Kishon Vijay Abraham I To: , , , CC: , Subject: [PATCH v3 3/3] PCI: host: pci-dra7xx: Idle the module by disabling MSE bit Date: Mon, 27 Jul 2015 11:54:54 +0530 Message-ID: <1437978294-22317-4-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1437978294-22317-1-git-send-email-kishon@ti.com> References: <1437978294-22317-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DRA7xx require MSE bit to be cleared to set the master in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe Controller Master Standby Behavior advises to use the clearing of the local MSE bit to set the master in standby. Without this some of the clocks do not idle). Cleared the MSE bit on suspend and enabled it back on resume. Clearing MSE bit is required to get clocks to be idled after suspend. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/pci/host/pci-dra7xx.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c index 7599201..7acc833 100644 --- a/drivers/pci/host/pci-dra7xx.c +++ b/drivers/pci/host/pci-dra7xx.c @@ -83,6 +83,17 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, writel(value, pcie->base + offset); } +static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset) +{ + return readl(pp->dbi_base + offset); +} + +static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset, + u32 value) +{ + writel(value, pp->dbi_base + offset); +} + static int dra7xx_pcie_link_up(struct pcie_port *pp) { struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); @@ -438,8 +449,12 @@ static int dra7xx_pcie_suspend(struct device *dev) { struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); struct pcie_port *pp = &dra7xx->pp; + u32 val; - dw_pcie_suspend_rc(pp); + /* clear MSE */ + val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND); + val &= ~PCI_COMMAND_MEMORY; + dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val); return 0; } @@ -448,8 +463,12 @@ static int dra7xx_pcie_resume(struct device *dev) { struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); struct pcie_port *pp = &dra7xx->pp; + u32 val; - dw_pcie_resume_rc(pp); + /* clear MSE */ + val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND); + val |= PCI_COMMAND_MEMORY; + dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val); return 0; }