From patchwork Thu Jul 30 07:46:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 6899641 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 038629F38B for ; Thu, 30 Jul 2015 07:49:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1A3C720511 for ; Thu, 30 Jul 2015 07:49:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F2D0E2051C for ; Thu, 30 Jul 2015 07:49:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754499AbbG3Hr2 (ORCPT ); Thu, 30 Jul 2015 03:47:28 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:50410 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753832AbbG3HrZ (ORCPT ); Thu, 30 Jul 2015 03:47:25 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id t6U7kwIX013398; Thu, 30 Jul 2015 02:46:58 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t6U7kwa8010064; Thu, 30 Jul 2015 02:46:58 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Thu, 30 Jul 2015 02:46:58 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t6U7kZVa006418; Thu, 30 Jul 2015 02:46:55 -0500 From: Kishon Vijay Abraham I To: , , , , , , CC: , , Subject: [PATCH 06/11] mmc: host: omap_hsmmc: set timing in the UHSMS field Date: Thu, 30 Jul 2015 13:16:29 +0530 Message-ID: <1438242394-25599-7-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1438242394-25599-1-git-send-email-kishon@ti.com> References: <1438242394-25599-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a separate function to set the UHSMS field to one of SDR104, SDR50, DDR50, SDR25 or SDR12 depending on the inserted SD card. This is required for tuning to succeed in the case of SDR104/HS200 or SDR50. Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/omap_hsmmc.c | 49 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 0452a8b..e0bd8df 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -114,6 +114,13 @@ /* AC12 */ #define AC12_V1V8_SIGEN (1 << 19) +#define AC12_UHSMC_MASK (7 << 16) +#define AC12_UHSMC_SDR12 (0 << 16) +#define AC12_UHSMC_SDR25 (1 << 16) +#define AC12_UHSMC_SDR50 (2 << 16) +#define AC12_UHSMC_SDR104 (3 << 16) +#define AC12_UHSMC_DDR50 (4 << 16) +#define AC12_UHSMC_RES (0x7 << 16) /* Interrupt masks for IE and ISE register */ #define CC_EN (1 << 0) @@ -198,6 +205,7 @@ struct omap_hsmmc_host { unsigned int dma_sg_idx; unsigned char bus_mode; unsigned char power_mode; + unsigned char timing; int suspended; u32 con; u32 hctl; @@ -1658,6 +1666,41 @@ static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) omap_hsmmc_start_command(host, req->cmd, req->data); } +static void omap_hsmmc_set_timing(struct omap_hsmmc_host *host) +{ + u32 val; + struct mmc_ios *ios = &host->mmc->ios; + + omap_hsmmc_stop_clock(host); + + val = OMAP_HSMMC_READ(host->base, AC12); + val &= ~AC12_UHSMC_MASK; + switch (ios->timing) { + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + val |= AC12_UHSMC_SDR104; + break; + case MMC_TIMING_UHS_DDR50: + val |= AC12_UHSMC_DDR50; + break; + case MMC_TIMING_UHS_SDR50: + val |= AC12_UHSMC_SDR50; + break; + case MMC_TIMING_UHS_SDR25: + val |= AC12_UHSMC_SDR25; + break; + case MMC_TIMING_UHS_SDR12: + val |= AC12_UHSMC_SDR12; + break; + default: + val |= AC12_UHSMC_RES; + break; + } + OMAP_HSMMC_WRITE(host->base, AC12, val); + + omap_hsmmc_start_clock(host); +} + /* Routine to configure clock values. Exposed API to core */ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -1706,6 +1749,11 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) omap_hsmmc_set_clock(host); + if (ios->timing != host->timing) { + omap_hsmmc_set_timing(host); + host->timing = ios->timing; + } + if (do_send_init_stream) send_init_stream(host); @@ -2194,6 +2242,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev) host->mapbase = res->start + pdata->reg_offset; host->base = base + pdata->reg_offset; host->power_mode = MMC_POWER_OFF; + host->timing = 0; host->next_data.cookie = 1; ret = omap_hsmmc_gpio_init(mmc, host, pdata);