Enable PSR in IvyBridge?
diff mbox

Message ID 1438892439.1448.0@smtp.gmail.com
State New
Headers show

Commit Message

harrykipper Aug. 6, 2015, 8:20 p.m. UTC
Hello,

I just discovered that Intel introduced PSR with IvyBridge, so I tried 
to enable it for my laptop, which has an eDP panel that supports psr. 
The patch is attached (all I do is enable all things IvyBridge, I am 
not familiar with the kernel at all, apologies if you see absurdities).

However, I had *some* success, I have:

Sink_Support: yes
Source_OK: yes
Enabled: yes
Active: yes
Busy frontbuffer bits: 0x000
Re-enable work scheduled: no
HW Enabled & Active bit: no
Link standby: no
Performance_Counter: 0

and so far I am only seeing one error, whenever the screen is turned 
on/off (at boot and when gnome blanks it to save power, for example). 
All the problems seem to be in intel_psr_exit() and intel_psr_flush(). 
I read in Rodrigo Vivi's blog that a psr test should exist in 
intel-gpu-tools, but I couldn't find it.

I am inclined to think that enabling psr for IvyBridge shouldn't be too 
hard for someone who knows what they are doing. If someone wants to 
take this on I will be happy to test and report bugs, although my 
hardware is fairly bizarre.

Best regards

 ------------[ cut here ]------------
kernel: WARNING: CPU: 3 PID: 726 at 
drivers/gpu/drm/i915/intel_psr.c:532 intel_psr_exit+0x152/0x160()
kernel: WARN_ON(!(val & EDP_PSR_ENABLE))
kernel: Modules linked in:
kernel:  fuse acpi_call(O) nls_iso8859_15 nls_cp850 vfat fat 
snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_cod
kernel: CPU: 3 PID: 726 Comm: Xorg Tainted: G     U     O    4.1.4-eDP 
#1
kernel: Hardware name: LENOVO 2324B14/2324B14, BIOS G2ETA3WW (2.63 ) 
02/05/2015
kernel:  ffffffff81718e70 000000000bfa939c ffffffff81718e70 
ffffffff815b820b
kernel:  ffff8800c50d7c50 ffffffff810709a7 ffff8802146c0000 
0000000000000000
kernel:  ffff880214a4a800 0000000000000000 ffff880214a4a800 
ffffffff81070a38
kernel: Call Trace:
kernel:  [<ffffffff815b820b>] ? dump_stack+0x47/0x67
kernel:  [<ffffffff810709a7>] ? warn_slowpath_common+0x77/0xb0
kernel:  [<ffffffff81070a38>] ? warn_slowpath_fmt+0x58/0x80
kernel:  [<ffffffff813c3ec2>] ? intel_psr_exit+0x152/0x160
kernel:  [<ffffffff813c4bf2>] ? intel_psr_invalidate+0x42/0x70
kernel:  [<ffffffff813c1268>] ? intel_fb_obj_invalidate+0xa8/0x110
kernel:  [<ffffffff8137bf07>] ? 
i915_gem_object_set_to_gtt_domain+0x127/0x150
kernel:  [<ffffffff8137ff33>] ? i915_gem_fault+0x1e3/0x3f0
kernel:  [<ffffffff811291ba>] ? __do_fault+0x4a/0xe0
kernel:  [<ffffffff811600e0>] ? __mem_cgroup_count_vm_event+0x10/0x70
kernel:  [<ffffffff8112d2f8>] ? handle_mm_fault+0x438/0x15b0
kernel:  [<ffffffff811899b3>] ? __fget+0x63/0xa0
kernel:  [<ffffffff8107a575>] ? recalc_sigpending+0x15/0x50
kernel:  [<ffffffff8107b1b8>] ? __set_task_blocked+0x38/0x90
kernel:  [<ffffffff8103f798>] ? __do_page_fault+0x158/0x3d0
kernel:  [<ffffffff8107db09>] ? SyS_rt_sigprocmask+0x89/0xd0
kernel:  [<ffffffff815c0342>] ? page_fault+0x22/0x30
kernel: ---[ end trace cb3b5b396afe8d4e ]---

Comments

Rodrigo Vivi Aug. 6, 2015, 11:56 p.m. UTC | #1
On Thu, Aug 6, 2015 at 1:20 PM harrykipper <harrykipper@gmail.com> wrote:

> Hello,
>
> I just discovered that Intel introduced PSR with IvyBridge, so I tried
>

Unfortunately this information is incorrect. There is no PSR on IVB. No
single mention in the specs here.


> to enable it for my laptop, which has an eDP panel that supports psr.


So yes, you might have a panel that supports PSR that came with IVB, but
PSR musts be supported on both sides, on panel and on gpu.


> The patch is attached (all I do is enable all things IvyBridge, I am
> not familiar with the kernel at all, apologies if you see absurdities).
>
> However, I had *some* success, I have:
>
> Sink_Support: yes
> Source_OK: yes
> Enabled: yes
> Active: yes
> Busy frontbuffer bits: 0x000
> Re-enable work scheduled: no
> HW Enabled & Active bit: no
>
actually this line here tells you didn't have success.


> Link standby: no
> Performance_Counter: 0
>
> and so far I am only seeing one error, whenever the screen is turned
> on/off (at boot and when gnome blanks it to save power, for example).
> All the problems seem to be in intel_psr_exit() and intel_psr_flush().
> I read in Rodrigo Vivi's blog that a psr test should exist in
> intel-gpu-tools, but I couldn't find it.
>

kms_psr_sink_crc and kms_frontbuffer_tracking can be used to test PSR, but
in your case it will probably just test a state machine entry exit with no
actual PSR entry/exit on the panel side.


>
> I am inclined to think that enabling psr for IvyBridge shouldn't be too
> hard for someone who knows what they are doing. If someone wants to
> take this on I will be happy to test and report bugs, although my
> hardware is fairly bizarre.
>

I would be happy to help if IVB had any PSR related patch... however this
is simply impossible.

Thanks for the interest,
Rodrigo


> Best regards


>  ------------[ cut here ]------------
> kernel: WARNING: CPU: 3 PID: 726 at
> drivers/gpu/drm/i915/intel_psr.c:532 intel_psr_exit+0x152/0x160()
> kernel: WARN_ON(!(val & EDP_PSR_ENABLE))
> kernel: Modules linked in:
> kernel:  fuse acpi_call(O) nls_iso8859_15 nls_cp850 vfat fat
> snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_cod
> kernel: CPU: 3 PID: 726 Comm: Xorg Tainted: G     U     O    4.1.4-eDP
> #1
> kernel: Hardware name: LENOVO 2324B14/2324B14, BIOS G2ETA3WW (2.63 )
> 02/05/2015
> kernel:  ffffffff81718e70 000000000bfa939c ffffffff81718e70
> ffffffff815b820b
> kernel:  ffff8800c50d7c50 ffffffff810709a7 ffff8802146c0000
> 0000000000000000
> kernel:  ffff880214a4a800 0000000000000000 ffff880214a4a800
> ffffffff81070a38
> kernel: Call Trace:
> kernel:  [<ffffffff815b820b>] ? dump_stack+0x47/0x67
> kernel:  [<ffffffff810709a7>] ? warn_slowpath_common+0x77/0xb0
> kernel:  [<ffffffff81070a38>] ? warn_slowpath_fmt+0x58/0x80
> kernel:  [<ffffffff813c3ec2>] ? intel_psr_exit+0x152/0x160
> kernel:  [<ffffffff813c4bf2>] ? intel_psr_invalidate+0x42/0x70
> kernel:  [<ffffffff813c1268>] ? intel_fb_obj_invalidate+0xa8/0x110
> kernel:  [<ffffffff8137bf07>] ?
> i915_gem_object_set_to_gtt_domain+0x127/0x150
> kernel:  [<ffffffff8137ff33>] ? i915_gem_fault+0x1e3/0x3f0
> kernel:  [<ffffffff811291ba>] ? __do_fault+0x4a/0xe0
> kernel:  [<ffffffff811600e0>] ? __mem_cgroup_count_vm_event+0x10/0x70
> kernel:  [<ffffffff8112d2f8>] ? handle_mm_fault+0x438/0x15b0
> kernel:  [<ffffffff811899b3>] ? __fget+0x63/0xa0
> kernel:  [<ffffffff8107a575>] ? recalc_sigpending+0x15/0x50
> kernel:  [<ffffffff8107b1b8>] ? __set_task_blocked+0x38/0x90
> kernel:  [<ffffffff8103f798>] ? __do_page_fault+0x158/0x3d0
> kernel:  [<ffffffff8107db09>] ? SyS_rt_sigprocmask+0x89/0xd0
> kernel:  [<ffffffff815c0342>] ? page_fault+0x22/0x30
> kernel: ---[ end trace cb3b5b396afe8d4e ]---
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
harrykipper Aug. 7, 2015, 7 a.m. UTC | #2
On Fri, 7 Aug, 2015 at 12:56 AM, Rodrigo Vivi <rodrigo.vivi@gmail.com> 
wrote:
> 
> 
> On Thu, Aug 6, 2015 at 1:20 PM harrykipper <harrykipper@gmail.com> 
> wrote:
>> Hello,
>> 
>> I just discovered that Intel introduced PSR with IvyBridge, so I 
>> tried
> 
> Unfortunately this information is incorrect. There is no PSR on IVB. 
> No single mention in the specs here.

Right. Sorry. I was misled by this Register article 
http://www.theregister.co.uk/2011/09/14/intel_demos_panel_self_refresh_display_tech/

It explicitly says "Intel will be supporting the tech in its 'Ivy 
Bridge' processors" :-(

I even had a feeling that after "activating" it the laptop was drawing 
less power :-D

Patch
diff mbox

diff -uNr linux-4.1.4-vanilla/drivers/gpu/drm/i915/i915_debugfs.c linux-4.1.4/drivers/gpu/drm/i915/i915_debugfs.c
--- linux-4.1.4-vanilla/drivers/gpu/drm/i915/i915_debugfs.c	2015-08-03 17:30:08.000000000 +0100
+++ linux-4.1.4/drivers/gpu/drm/i915/i915_debugfs.c	2015-08-06 12:10:26.335922540 +0100
@@ -2269,7 +2269,7 @@ 
 	seq_printf(m, "Re-enable work scheduled: %s\n",
 		   yesno(work_busy(&dev_priv->psr.work.work)));
 
-	if (HAS_DDI(dev))
+	if (HAS_DDI(dev) || IS_IVYBRIDGE(dev))
 		enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
 	else {
 		for_each_pipe(dev_priv, pipe) {
@@ -2282,7 +2282,7 @@ 
 	}
 	seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
 
-	if (!HAS_DDI(dev))
+	if (!HAS_DDI(dev) || !IS_IVYBRIDGE(dev))
 		for_each_pipe(dev_priv, pipe) {
 			if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 			    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
@@ -2294,7 +2294,7 @@ 
 		   yesno((bool)dev_priv->psr.link_standby));
 
 	/* CHV PSR has no kind of performance counter */
-	if (HAS_DDI(dev)) {
+	if (HAS_DDI(dev) || IS_IVYBRIDGE(dev)) {
 		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
 			EDP_PSR_PERF_CNT_MASK;
 
diff -uNr linux-4.1.4-vanilla/drivers/gpu/drm/i915/i915_drv.h linux-4.1.4/drivers/gpu/drm/i915/i915_drv.h
--- linux-4.1.4-vanilla/drivers/gpu/drm/i915/i915_drv.h	2015-08-03 17:30:08.000000000 +0100
+++ linux-4.1.4/drivers/gpu/drm/i915/i915_drv.h	2015-08-06 09:43:32.558967848 +0100
@@ -2398,7 +2398,7 @@ 
 
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_IVYBRIDGE(dev) || IS_BROADWELL(dev) || \
 				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
 				 IS_SKYLAKE(dev))
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
diff -uNr linux-4.1.4-vanilla/drivers/gpu/drm/i915/intel_dp.c linux-4.1.4/drivers/gpu/drm/i915/intel_dp.c
--- linux-4.1.4-vanilla/drivers/gpu/drm/i915/intel_dp.c	2015-08-03 17:30:08.000000000 +0100
+++ linux-4.1.4/drivers/gpu/drm/i915/intel_dp.c	2015-08-06 12:58:22.562701511 +0100
 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
@@ -2291,9 +2290,6 @@ 
 	if (crtc->config->has_audio)
 		intel_audio_codec_disable(encoder);
 
-	if (HAS_PSR(dev) && (!HAS_DDI(dev)))
+	if (HAS_PSR(dev) && (!HAS_DDI(dev) || !IS_IVYBRIDGE(dev)))
		intel_psr_disable(intel_dp);

 	/* Make sure the panel is off before trying to change the mode. But also
 	 * ensure that we have vdd while we switch off the panel. */
 	intel_edp_panel_vdd_on(intel_dp);
@@ -2511,6 +2507,7 @@ 
 
 	intel_enable_dp(encoder);
 	intel_edp_backlight_on(intel_dp);
+	if IS_IVYBRIDGE(dev) 
+		intel_psr_enable(intel_dp);
 }
  
diff -uNr linux-4.1.4-vanilla/drivers/gpu/drm/i915/intel_psr.c linux-4.1.4/drivers/gpu/drm/i915/intel_psr.c
--- linux-4.1.4-vanilla/drivers/gpu/drm/i915/intel_psr.c	2015-08-03 17:30:08.000000000 +0100
+++ linux-4.1.4/drivers/gpu/drm/i915/intel_psr.c	2015-08-06 12:28:49.086035280 +0100
@@ -309,7 +309,7 @@ 
 	lockdep_assert_held(&dev_priv->psr.lock);
 
 	/* Enable/Re-enable PSR on the host */
-	if (HAS_DDI(dev))
+	if (HAS_DDI(dev) || INTEL_INFO(dev)->gen >= 7)
 		/* On HSW+ after we enable PSR on source it will activate it
 		 * as soon as it match configure idle_frame count. So
 		 * we just actually enable it here on activation time.
@@ -361,7 +361,7 @@ 
 
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
-	if (HAS_DDI(dev)) {
+	if (HAS_DDI(dev) || INTEL_INFO(dev)->gen >= 7) {
 		hsw_psr_setup_vsc(intel_dp);
 
 		/* Avoid continuous PSR exit by masking memup and hpd */
@@ -459,7 +459,7 @@ 
 		return;
 	}
 
-	if (HAS_DDI(dev))
+	if (HAS_DDI(dev) || INTEL_INFO(dev)->gen >= 7)
 		hsw_psr_disable(intel_dp);
 	else
 		vlv_psr_disable(intel_dp);
@@ -483,7 +483,7 @@ 
 	 * PSR might take some time to get fully disabled
 	 * and be ready for re-enable.
 	 */
-	if (HAS_DDI(dev_priv->dev)) {
+	if (HAS_DDI(dev_priv->dev) || INTEL_INFO(dev_priv->dev)->gen >= 7) {
 		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
 			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
 			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
@@ -526,7 +526,7 @@ 
 	if (!dev_priv->psr.active)
 		return;
 
-	if (HAS_DDI(dev)) {
+	if (HAS_DDI(dev) || INTEL_INFO(dev)->gen >= 7) {
 		val = I915_READ(EDP_PSR_CTL(dev));
 
 		WARN_ON(!(val & EDP_PSR_ENABLE));
@@ -630,7 +630,7 @@ 
 	 * software for all flushes, not just when we've seen a preceding
 	 * invalidation through frontbuffer rendering.
 	 */
-	if (IS_HASWELL(dev) &&
+	if (IS_HASWELL(dev) || IS_IVYBRIDGE(dev) &&
 	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
 		intel_psr_exit(dev);
 
@@ -640,7 +640,7 @@ 
 	 * invalidating. Which means we need to manually fake this in
 	 * software for all flushes, not just when we've seen a preceding
 	 * invalidation through frontbuffer rendering. */
-	if (!HAS_DDI(dev))
+	if (!HAS_DDI(dev) || !IS_IVYBRIDGE(dev)
 		intel_psr_exit(dev);
 
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)