diff -uNr linux-4.1.4-vanilla/drivers/gpu/drm/i915/i915_debugfs.c linux-4.1.4/drivers/gpu/drm/i915/i915_debugfs.c
--- linux-4.1.4-vanilla/drivers/gpu/drm/i915/i915_debugfs.c	2015-08-03 17:30:08.000000000 +0100
+++ linux-4.1.4/drivers/gpu/drm/i915/i915_debugfs.c	2015-08-06 12:10:26.335922540 +0100
@@ -2269,7 +2269,7 @@
 	seq_printf(m, "Re-enable work scheduled: %s\n",
 		   yesno(work_busy(&dev_priv->psr.work.work)));
 
-	if (HAS_DDI(dev))
+	if (HAS_DDI(dev) || IS_IVYBRIDGE(dev))
 		enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
 	else {
 		for_each_pipe(dev_priv, pipe) {
@@ -2282,7 +2282,7 @@
 	}
 	seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
 
-	if (!HAS_DDI(dev))
+	if (!HAS_DDI(dev) || !IS_IVYBRIDGE(dev))
 		for_each_pipe(dev_priv, pipe) {
 			if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
 			    (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
@@ -2294,7 +2294,7 @@
 		   yesno((bool)dev_priv->psr.link_standby));
 
 	/* CHV PSR has no kind of performance counter */
-	if (HAS_DDI(dev)) {
+	if (HAS_DDI(dev) || IS_IVYBRIDGE(dev)) {
 		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
 			EDP_PSR_PERF_CNT_MASK;
 
diff -uNr linux-4.1.4-vanilla/drivers/gpu/drm/i915/i915_drv.h linux-4.1.4/drivers/gpu/drm/i915/i915_drv.h
--- linux-4.1.4-vanilla/drivers/gpu/drm/i915/i915_drv.h	2015-08-03 17:30:08.000000000 +0100
+++ linux-4.1.4/drivers/gpu/drm/i915/i915_drv.h	2015-08-06 09:43:32.558967848 +0100
@@ -2398,7 +2398,7 @@
 
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
+#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_IVYBRIDGE(dev) || IS_BROADWELL(dev) || \
 				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
 				 IS_SKYLAKE(dev))
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
diff -uNr linux-4.1.4-vanilla/drivers/gpu/drm/i915/intel_dp.c linux-4.1.4/drivers/gpu/drm/i915/intel_dp.c
--- linux-4.1.4-vanilla/drivers/gpu/drm/i915/intel_dp.c	2015-08-03 17:30:08.000000000 +0100
+++ linux-4.1.4/drivers/gpu/drm/i915/intel_dp.c	2015-08-06 12:58:22.562701511 +0100
 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
@@ -2291,9 +2290,6 @@
 	if (crtc->config->has_audio)
 		intel_audio_codec_disable(encoder);
 
-	if (HAS_PSR(dev) && (!HAS_DDI(dev)))
+	if (HAS_PSR(dev) && (!HAS_DDI(dev) || !IS_IVYBRIDGE(dev)))
		intel_psr_disable(intel_dp);

 	/* Make sure the panel is off before trying to change the mode. But also
 	 * ensure that we have vdd while we switch off the panel. */
 	intel_edp_panel_vdd_on(intel_dp);
@@ -2511,6 +2507,7 @@
 
 	intel_enable_dp(encoder);
 	intel_edp_backlight_on(intel_dp);
+	if IS_IVYBRIDGE(dev) 
+		intel_psr_enable(intel_dp);
 }
  
diff -uNr linux-4.1.4-vanilla/drivers/gpu/drm/i915/intel_psr.c linux-4.1.4/drivers/gpu/drm/i915/intel_psr.c
--- linux-4.1.4-vanilla/drivers/gpu/drm/i915/intel_psr.c	2015-08-03 17:30:08.000000000 +0100
+++ linux-4.1.4/drivers/gpu/drm/i915/intel_psr.c	2015-08-06 12:28:49.086035280 +0100
@@ -309,7 +309,7 @@
 	lockdep_assert_held(&dev_priv->psr.lock);
 
 	/* Enable/Re-enable PSR on the host */
-	if (HAS_DDI(dev))
+	if (HAS_DDI(dev) || INTEL_INFO(dev)->gen >= 7)
 		/* On HSW+ after we enable PSR on source it will activate it
 		 * as soon as it match configure idle_frame count. So
 		 * we just actually enable it here on activation time.
@@ -361,7 +361,7 @@
 
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
-	if (HAS_DDI(dev)) {
+	if (HAS_DDI(dev) || INTEL_INFO(dev)->gen >= 7) {
 		hsw_psr_setup_vsc(intel_dp);
 
 		/* Avoid continuous PSR exit by masking memup and hpd */
@@ -459,7 +459,7 @@
 		return;
 	}
 
-	if (HAS_DDI(dev))
+	if (HAS_DDI(dev) || INTEL_INFO(dev)->gen >= 7)
 		hsw_psr_disable(intel_dp);
 	else
 		vlv_psr_disable(intel_dp);
@@ -483,7 +483,7 @@
 	 * PSR might take some time to get fully disabled
 	 * and be ready for re-enable.
 	 */
-	if (HAS_DDI(dev_priv->dev)) {
+	if (HAS_DDI(dev_priv->dev) || INTEL_INFO(dev_priv->dev)->gen >= 7) {
 		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
 			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
 			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
@@ -526,7 +526,7 @@
 	if (!dev_priv->psr.active)
 		return;
 
-	if (HAS_DDI(dev)) {
+	if (HAS_DDI(dev) || INTEL_INFO(dev)->gen >= 7) {
 		val = I915_READ(EDP_PSR_CTL(dev));
 
 		WARN_ON(!(val & EDP_PSR_ENABLE));
@@ -630,7 +630,7 @@
 	 * software for all flushes, not just when we've seen a preceding
 	 * invalidation through frontbuffer rendering.
 	 */
-	if (IS_HASWELL(dev) &&
+	if (IS_HASWELL(dev) || IS_IVYBRIDGE(dev) &&
 	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
 		intel_psr_exit(dev);
 
@@ -640,7 +640,7 @@
 	 * invalidating. Which means we need to manually fake this in
 	 * software for all flushes, not just when we've seen a preceding
 	 * invalidation through frontbuffer rendering. */
-	if (!HAS_DDI(dev))
+	if (!HAS_DDI(dev) || !IS_IVYBRIDGE(dev)
 		intel_psr_exit(dev);
 
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
