| Message ID | 1438938752-31010-20-git-send-email-rogerq@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index ce11b0f..3fb1ced 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -573,6 +573,7 @@ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&crossbar_mpu>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 8f1e25b..a4ab66d 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1369,6 +1369,10 @@ gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 8037384..fc0677a 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -386,6 +386,7 @@ * SW5.9 (GPMC_WPN) = OFF (HIGH) */ reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&crossbar_mpu>; ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>;
The GPMC driver now implements gpiochip and irqchip so enable gpio-controller and interrupt-controller properties. With this the interrupt parent of NAND node changes so fix it accordingly. Signed-off-by: Roger Quadros <rogerq@ti.com> --- arch/arm/boot/dts/dra7-evm.dts | 1 + arch/arm/boot/dts/dra7.dtsi | 4 ++++ arch/arm/boot/dts/dra72-evm.dts | 1 + 3 files changed, 6 insertions(+)