From patchwork Mon Aug 10 13:25:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhichao Huang X-Patchwork-Id: 6984231 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4BA5F9F344 for ; Mon, 10 Aug 2015 13:27:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C36E2205FF for ; Mon, 10 Aug 2015 13:27:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E2ECA204A2 for ; Mon, 10 Aug 2015 13:27:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754385AbbHJN1q (ORCPT ); Mon, 10 Aug 2015 09:27:46 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:34713 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753296AbbHJN1i (ORCPT ); Mon, 10 Aug 2015 09:27:38 -0400 Received: by pawu10 with SMTP id u10so140681409paw.1 for ; Mon, 10 Aug 2015 06:27:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2TtCpoJHp/qiJnXflnw82PiSlTMUeyKnvCore7LMJ9g=; b=RIVVBDx+JhpYBcMWK8Q+FyKRGnDF58w48epu23PkmFucAS7CoPzj8zabVCjEnjspxR 8mu0nXQ7e4HCeDwDTgrVwQdmCHgxD/uqEAgN/8tIYzGWMEfjyGox+fgBT0eSS3wrrNJb Cx2mkfMRK4y+5G/MkqZBwlgLIL8UMKamZlZXqNGGH+i7pJGyttKkK385y4An/ozHIj4k dY0YLUeQFOmiAYJ8YhbuExNhg556ymNIT/+AcLVtLFgv/LikptcxMg3puLyvaiW4iTq5 eNoAPzxxe1tG5woJZOQeKSH00FvLXy48DHxc8vhdPERtnitnCdM1ZFOy2Tb/Mihi4BZ9 4ymw== X-Gm-Message-State: ALoCoQlh6T/KDnBiDCNPWLFD2hZSF3AlTqfBBIookbHLeZrXEQaeZD2d5T40HC4qBtGnsylT9VbF X-Received: by 10.66.190.168 with SMTP id gr8mr44695077pac.22.1439213258159; Mon, 10 Aug 2015 06:27:38 -0700 (PDT) Received: from localhost ([199.168.112.128]) by smtp.gmail.com with ESMTPSA id ob15sm16167378pdb.52.2015.08.10.06.27.36 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 10 Aug 2015 06:27:37 -0700 (PDT) From: Zhichao Huang To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, alex.bennee@linaro.org, will.deacon@arm.com Cc: huangzhichao@huawei.com, Zhichao Huang Subject: [PATCH v4 07/15] KVM: arm: add trap handlers for 64-bit debug registers Date: Mon, 10 Aug 2015 21:25:59 +0800 Message-Id: <1439213167-8988-8-git-send-email-zhichao.huang@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1439213167-8988-1-git-send-email-zhichao.huang@linaro.org> References: <1439213167-8988-1-git-send-email-zhichao.huang@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add handlers for all the 64-bit debug registers. There is an overlap between 32 and 64bit registers. Make sure that 64-bit registers preceding 32-bit ones. Signed-off-by: Zhichao Huang Reviewed-by: Christoffer Dall --- arch/arm/kvm/coproc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index b3627f0..2164f4e 100644 --- a/arch/arm/kvm/coproc.c +++ b/arch/arm/kvm/coproc.c @@ -440,6 +440,12 @@ static const struct coproc_reg cp15_regs[] = { * Trapped cp14 registers. We generally ignore most of the external * debug, on the principle that they don't really make sense to a * guest. Revisit this one day, should this principle change. + * + * CRn denotes the primary register number, but is copied to the CRm in the + * user space API for 64-bit register access in line with the terminology used + * in the ARM ARM. + * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit + * registers preceding 32-bit ones. */ static const struct coproc_reg cp14_regs[] = { /* DBGIDR */ @@ -447,10 +453,14 @@ static const struct coproc_reg cp14_regs[] = { /* DBGDTRRXext */ { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, trap_raz_wi }, DBG_BCR_BVR_WCR_WVR(0), + /* DBGDRAR (64bit) */ + { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is64, trap_raz_wi }, /* DBGDSCRint */ { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, trap_dbgdscr, NULL, cp14_DBGDSCRext }, DBG_BCR_BVR_WCR_WVR(1), + /* DBGDSAR (64bit) */ + { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is64, trap_raz_wi }, /* DBGDSCRext */ { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, trap_debug32, reset_val, cp14_DBGDSCRext, 0 },