From patchwork Mon Aug 10 13:26:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhichao Huang X-Patchwork-Id: 6984251 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3AE31C05AC for ; Mon, 10 Aug 2015 13:28:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 211122026F for ; Mon, 10 Aug 2015 13:28:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E9FDB20483 for ; Mon, 10 Aug 2015 13:28:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752947AbbHJN2W (ORCPT ); Mon, 10 Aug 2015 09:28:22 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:33483 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751684AbbHJN2V (ORCPT ); Mon, 10 Aug 2015 09:28:21 -0400 Received: by pabyb7 with SMTP id yb7so106849349pab.0 for ; Mon, 10 Aug 2015 06:28:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rVTuM+0qFCqEHfAmsmfo8eOnjWSOMuPLVfJdtJww6kU=; b=YfCvgC2jz+VncDEy2bvzVIkm0PkA76CuA9mqsAUR+p/roXn+df+Ql0XucSbrM8OOLw qt9s93wWN2QjJiDHz7+SFS3vshzNyf8IYua483DH4q6YRwZ4K6Uel7kaG1d97pqFcEov PleB9Ygiwwq8j8BhqJ9r6mVEQWkd0n5axZJDiAU5MehYBaAThng+S/HFTUlLx55NvGpt 2HQCrSPD2zPqDtceoW4cNoInM1r0731LYp72185kVk4P7MSUUkOzbjlGTcRwOyMfod5W D8l+XQjWDKI9gwKXFIstLg3l7xl7GF1z/tyDZ71fIJruz6KC7jDXqDzVNtwOR2VonKC+ ojEg== X-Gm-Message-State: ALoCoQlihK0U1Ql0FpU7sCblPptwegnRJFCr6Tuj/cym80cHCeEvJt/TLiRLZWugmTdFYa74cwZs X-Received: by 10.68.248.102 with SMTP id yl6mr45009001pbc.66.1439213301370; Mon, 10 Aug 2015 06:28:21 -0700 (PDT) Received: from localhost ([199.168.112.128]) by smtp.gmail.com with ESMTPSA id ob4sm19975424pbb.40.2015.08.10.06.28.18 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 10 Aug 2015 06:28:20 -0700 (PDT) From: Zhichao Huang To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, alex.bennee@linaro.org, will.deacon@arm.com Cc: huangzhichao@huawei.com, Zhichao Huang Subject: [PATCH v4 10/15] KVM: arm: implement world switch for debug registers Date: Mon, 10 Aug 2015 21:26:02 +0800 Message-Id: <1439213167-8988-11-git-send-email-zhichao.huang@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1439213167-8988-1-git-send-email-zhichao.huang@linaro.org> References: <1439213167-8988-1-git-send-email-zhichao.huang@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Implement switching of the debug registers. While the number of registers is massive, CPUs usually don't implement them all (A15 has 6 breakpoints and 4 watchpoints, which gives us a total of 22 registers "only"). Signed-off-by: Zhichao Huang --- arch/arm/kvm/interrupts_head.S | 170 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 159 insertions(+), 11 deletions(-) diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S index 7ac5e51..b9e7410 100644 --- a/arch/arm/kvm/interrupts_head.S +++ b/arch/arm/kvm/interrupts_head.S @@ -5,6 +5,7 @@ #define VCPU_USR_SP (VCPU_USR_REG(13)) #define VCPU_USR_LR (VCPU_USR_REG(14)) #define CP15_OFFSET(_cp15_reg_idx) (VCPU_CP15 + (_cp15_reg_idx * 4)) +#define CP14_OFFSET(_cp14_reg_idx) ((_cp14_reg_idx) * 4) /* * Many of these macros need to access the VCPU structure, which is always @@ -239,6 +240,136 @@ vcpu .req r0 @ vcpu pointer always in r0 save_guest_regs_mode irq, #VCPU_IRQ_REGS .endm +/* Assume r10/r11/r12 are in use, clobbers r2-r3 */ +.macro cp14_read_and_str base Op2 cp14_reg0 skip_num + adr r3, 1f + add r3, r3, \skip_num, lsl #3 + bx r3 +1: + mrc p14, 0, r2, c0, c15, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+15)] + mrc p14, 0, r2, c0, c14, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+14)] + mrc p14, 0, r2, c0, c13, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+13)] + mrc p14, 0, r2, c0, c12, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+12)] + mrc p14, 0, r2, c0, c11, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+11)] + mrc p14, 0, r2, c0, c10, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+10)] + mrc p14, 0, r2, c0, c9, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+9)] + mrc p14, 0, r2, c0, c8, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+8)] + mrc p14, 0, r2, c0, c7, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+7)] + mrc p14, 0, r2, c0, c6, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+6)] + mrc p14, 0, r2, c0, c5, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+5)] + mrc p14, 0, r2, c0, c4, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+4)] + mrc p14, 0, r2, c0, c3, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+3)] + mrc p14, 0, r2, c0, c2, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+2)] + mrc p14, 0, r2, c0, c1, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0+1)] + mrc p14, 0, r2, c0, c0, \Op2 + str r2, [\base, #CP14_OFFSET(\cp14_reg0)] +.endm + +/* Assume r11/r12 are in use, clobbers r2-r3 */ +.macro cp14_ldr_and_write base Op2 cp14_reg0 skip_num + adr r3, 1f + add r3, r3, \skip_num, lsl #3 + bx r3 +1: + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+15)] + mcr p14, 0, r2, c0, c15, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+14)] + mcr p14, 0, r2, c0, c14, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+13)] + mcr p14, 0, r2, c0, c13, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+12)] + mcr p14, 0, r2, c0, c12, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+11)] + mcr p14, 0, r2, c0, c11, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+10)] + mcr p14, 0, r2, c0, c10, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+9)] + mcr p14, 0, r2, c0, c9, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+8)] + mcr p14, 0, r2, c0, c8, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+7)] + mcr p14, 0, r2, c0, c7, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+6)] + mcr p14, 0, r2, c0, c6, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+5)] + mcr p14, 0, r2, c0, c5, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+4)] + mcr p14, 0, r2, c0, c4, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+3)] + mcr p14, 0, r2, c0, c3, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+2)] + mcr p14, 0, r2, c0, c2, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0+1)] + mcr p14, 0, r2, c0, c1, \Op2 + ldr r2, [\base, #CP14_OFFSET(\cp14_reg0)] + mcr p14, 0, r2, c0, c0, \Op2 +.endm + +/* Get extract number of BRPs and WRPs. Saved in r11/r12 */ +.macro read_hw_dbg_num + mrc p14, 0, r2, c0, c0, 0 + ubfx r11, r2, #24, #4 + add r11, r11, #1 @ Extract BRPs + ubfx r12, r2, #28, #4 + add r12, r12, #1 @ Extract WRPs + mov r2, #16 + sub r11, r2, r11 @ How many BPs to skip + sub r12, r2, r12 @ How many WPs to skip +.endm + +/* Reads cp14 registers from hardware. + * Writes cp14 registers in-order to the CP14 struct pointed to by r10 + * + * Assumes vcpu pointer in vcpu reg + * + * Clobbers r2-r12 + */ +.macro save_debug_state + read_hw_dbg_num + cp14_read_and_str r10, 4, cp14_DBGBVR0, r11 + cp14_read_and_str r10, 5, cp14_DBGBCR0, r11 + cp14_read_and_str r10, 6, cp14_DBGWVR0, r12 + cp14_read_and_str r10, 7, cp14_DBGWCR0, r12 + + /* DBGDSCR reg */ + mrc p14, 0, r2, c0, c1, 0 + str r2, [r10, #CP14_OFFSET(cp14_DBGDSCRext)] +.endm + +/* Reads cp14 registers in-order from the CP14 struct pointed to by r10 + * Writes cp14 registers to hardware. + * + * Assumes vcpu pointer in vcpu reg + * + * Clobbers r2-r12 + */ +.macro restore_debug_state + read_hw_dbg_num + cp14_ldr_and_write r10, 4, cp14_DBGBVR0, r11 + cp14_ldr_and_write r10, 5, cp14_DBGBCR0, r11 + cp14_ldr_and_write r10, 6, cp14_DBGWVR0, r12 + cp14_ldr_and_write r10, 7, cp14_DBGWCR0, r12 + + /* DBGDSCR reg */ + ldr r2, [r10, #CP14_OFFSET(cp14_DBGDSCRext)] + mcr p14, 0, r2, c0, c2, 2 +.endm + /* Reads cp14/cp15 registers from hardware and stores them in memory * @store_to_vcpu: If 0, registers are written in-order to the stack, * otherwise to the VCPU struct pointed to by vcpup @@ -248,11 +379,17 @@ vcpu .req r0 @ vcpu pointer always in r0 * Clobbers r2 - r12 */ .macro read_coproc_state store_to_vcpu - .if \store_to_vcpu == 0 - mrc p14, 0, r2, c0, c1, 0 @ DBGDSCR - push {r2} + .if \store_to_vcpu == 1 + add r10, vcpu, #VCPU_CP14 + .else + add r10, vcpu, #VCPU_HOST_CONTEXT + ldr r10, [r10] + add r10, r10, #VCPU_CP14_HOST .endif + /* Assumes r10 pointer in cp14 regs */ + bl __save_debug_state + mrc p15, 0, r2, c1, c0, 0 @ SCTLR mrc p15, 0, r3, c1, c0, 2 @ CPACR mrc p15, 0, r4, c2, c0, 2 @ TTBCR @@ -331,6 +468,17 @@ vcpu .req r0 @ vcpu pointer always in r0 * Assumes vcpu pointer in vcpu reg */ .macro write_coproc_state read_from_vcpu + .if \read_from_vcpu == 1 + add r10, vcpu, #VCPU_CP14 + .else + add r10, vcpu, #VCPU_HOST_CONTEXT + ldr r10, [r10] + add r10, r10, #VCPU_CP14_HOST + .endif + + /* Assumes r10 pointer in cp14 regs */ + bl __restore_debug_state + .if \read_from_vcpu == 0 pop {r2,r4-r7} .else @@ -399,14 +547,6 @@ vcpu .req r0 @ vcpu pointer always in r0 mcr p15, 0, r10, c10, c2, 0 @ PRRR mcr p15, 0, r11, c10, c2, 1 @ NMRR mcr p15, 2, r12, c0, c0, 0 @ CSSELR - - .if \read_from_vcpu == 0 - pop {r2} - .else - mov r2, #0 - .endif - - mcr p14, 0, r2, c0, c2, 2 @ DBGDSCR .endm /* @@ -657,3 +797,11 @@ ARM_BE8(rev r6, r6 ) .macro load_vcpu mrc p15, 4, vcpu, c13, c0, 2 @ HTPIDR .endm + +__save_debug_state: + save_debug_state + bx lr + +__restore_debug_state: + restore_debug_state + bx lr