[3/4] drm/i915: Avoid TP3 on CHV
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Message ID 1439813711-2438-4-git-send-email-sivakumar.thulasimani@intel.com
State New
Headers show

Commit Message

Sivakumar Thulasimani Aug. 17, 2015, 12:15 p.m. UTC
From: "Thulasimani,Sivakumar" <sivakumar.thulasimani@intel.com>

This patch removes TP3 support on CHV since there is no support
for HBR2 on this platform.

Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |   24 +++++++++++++++++-------
 1 file changed, 17 insertions(+), 7 deletions(-)

Comments

Jani Nikula Aug. 17, 2015, 12:25 p.m. UTC | #1
On Mon, 17 Aug 2015, Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> wrote:
> From: "Thulasimani,Sivakumar" <sivakumar.thulasimani@intel.com>
>
> This patch removes TP3 support on CHV since there is no support
> for HBR2 on this platform.
>
> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c |   24 +++++++++++++++++-------
>  1 file changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 475d8cb..03523b3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1207,6 +1207,20 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>  	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
>  }
>  
> +static bool intel_dp_is_hbr2_supported(struct drm_device *dev)

Sorry to be a nitpicker, but I really like how we've started
distinguishing source and sink in such helpers in intel_dp.c, for
example intel_dp_source_rates vs. intel_dp_sink_rates. Similarly I think
you should name this intel_dp_source_supports_hbr2.

BR,
Jani.

> +{
> +	/* WaDisableHBR2:skl */
> +	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
> +		return false;
> +
> +	if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
> +	    (INTEL_INFO(dev)->gen >= 9))
> +		return true;
> +	else
> +		return false;
> +}
> +
> +
>  static int
>  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>  {
> @@ -1220,12 +1234,8 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>  
>  	*source_rates = default_rates;
>  
> -	/* WaDisableHBR2:skl */
> -	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
> -		return (DP_LINK_BW_2_7 >> 3) + 1;
> -
> -	if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
> -	    (INTEL_INFO(dev)->gen >= 9))
> +	/* This depends on the fact that 5.4 is last value in the array */
> +	if (intel_dp_is_hbr2_supported(dev))
>  		return (DP_LINK_BW_5_4 >> 3) + 1;
>  	else
>  		return (DP_LINK_BW_2_7 >> 3) + 1;
> @@ -3926,7 +3936,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
>  	/* Training Pattern 3 support, both source and sink */
>  	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
>  	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
> -	    (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
> +	    intel_dp_is_hbr2_supported(dev)) {
>  		intel_dp->use_tps3 = true;
>  		DRM_DEBUG_KMS("Displayport TPS3 supported\n");
>  	} else
> -- 
> 1.7.9.5
>

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 475d8cb..03523b3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1207,6 +1207,20 @@  intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
 }
 
+static bool intel_dp_is_hbr2_supported(struct drm_device *dev)
+{
+	/* WaDisableHBR2:skl */
+	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
+		return false;
+
+	if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
+	    (INTEL_INFO(dev)->gen >= 9))
+		return true;
+	else
+		return false;
+}
+
+
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
@@ -1220,12 +1234,8 @@  intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 
 	*source_rates = default_rates;
 
-	/* WaDisableHBR2:skl */
-	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
-		return (DP_LINK_BW_2_7 >> 3) + 1;
-
-	if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
-	    (INTEL_INFO(dev)->gen >= 9))
+	/* This depends on the fact that 5.4 is last value in the array */
+	if (intel_dp_is_hbr2_supported(dev))
 		return (DP_LINK_BW_5_4 >> 3) + 1;
 	else
 		return (DP_LINK_BW_2_7 >> 3) + 1;
@@ -3926,7 +3936,7 @@  intel_dp_get_dpcd(struct intel_dp *intel_dp)
 	/* Training Pattern 3 support, both source and sink */
 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
 	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
-	    (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
+	    intel_dp_is_hbr2_supported(dev)) {
 		intel_dp->use_tps3 = true;
 		DRM_DEBUG_KMS("Displayport TPS3 supported\n");
 	} else