| Message ID | 1440608246-17010-1-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Aug 26, 2015 at 06:57:26PM +0200, Daniel Vetter wrote: > Forgot to do that in > > commit d328c9d78d64ca11e744fe227096990430a88477 > Author: Daniel Vetter <daniel.vetter@ffwll.ch> > Date: Fri Apr 10 16:22:37 2015 +0200 > > drm/i915: Select starting pipe bpp irrespective or the primary plane > > and it's confusing. Fix it. > > Cc: Jesse Barnes <jbarnes@virtuousgeek.org> > Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Merged to dinq with Jesse's irc ack. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 384c575ae65f..957a3680381c 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -12112,10 +12112,6 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, > (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) > pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; > > - /* Compute a starting value for pipe_config->pipe_bpp taking the source > - * plane pixel format and any sink constraints into account. Returns the > - * source plane bpp so that dithering can be selected on mismatches > - * after encoders and crtc also have had their say. */ > base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), > pipe_config); > if (base_bpp < 0) > @@ -12184,7 +12180,7 @@ encoder_retry: > /* Dithering seems to not pass-through bits correctly when it should, so > * only enable it on 6bpc panels. */ > pipe_config->dither = pipe_config->pipe_bpp == 6*3; > - DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", > + DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", > base_bpp, pipe_config->pipe_bpp, pipe_config->dither); > > fail: > -- > 2.5.0 >
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 384c575ae65f..957a3680381c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12112,10 +12112,6 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; - /* Compute a starting value for pipe_config->pipe_bpp taking the source - * plane pixel format and any sink constraints into account. Returns the - * source plane bpp so that dithering can be selected on mismatches - * after encoders and crtc also have had their say. */ base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), pipe_config); if (base_bpp < 0) @@ -12184,7 +12180,7 @@ encoder_retry: /* Dithering seems to not pass-through bits correctly when it should, so * only enable it on 6bpc panels. */ pipe_config->dither = pipe_config->pipe_bpp == 6*3; - DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", + DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", base_bpp, pipe_config->pipe_bpp, pipe_config->dither); fail:
Forgot to do that in commit d328c9d78d64ca11e744fe227096990430a88477 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Fri Apr 10 16:22:37 2015 +0200 drm/i915: Select starting pipe bpp irrespective or the primary plane and it's confusing. Fix it. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-)