From patchwork Wed Sep 2 16:20:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 7113061 Return-Path: X-Original-To: patchwork-linux-parisc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7FB6BBEEC1 for ; Wed, 2 Sep 2015 16:20:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9572920515 for ; Wed, 2 Sep 2015 16:20:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 60EDD204E2 for ; Wed, 2 Sep 2015 16:20:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752763AbbIBQUL (ORCPT ); Wed, 2 Sep 2015 12:20:11 -0400 Received: from mout.gmx.net ([212.227.17.22]:50310 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752464AbbIBQUL (ORCPT ); Wed, 2 Sep 2015 12:20:11 -0400 Received: from ls3530.box ([92.203.6.179]) by mail.gmx.com (mrgmx101) with ESMTPSA (Nemesis) id 0Lqm3a-1Z1ysQ1Kkc-00eKIO; Wed, 02 Sep 2015 18:20:04 +0200 Date: Wed, 2 Sep 2015 18:20:00 +0200 From: Helge Deller To: linux-parisc@vger.kernel.org Cc: John David Anglin , James Bottomley Subject: [PATCH] parisc: adjust L1_CACHE_BYTES to 128 bytes on PA8800 and PA8900 CPUs Message-ID: <20150902162000.GC2444@ls3530.box> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-Provags-ID: V03:K0:skq195tlu2ZjzmMLV1wMTzeKFXnrGj7l5iH9hIsqfA7oC73bbnA xd715EcEUtb5UMAjvUGgtHxEVav6w2b6JVgjLn5Wr1ENzEwWbFI+IAOL4ZjENJUH0oahu33 7SitvFH+Jz05/qPLJg2wS65dYqqiGJucs640OMJ1pVx3vhztD4WSRkPXt7pOUQ2VP4T3bmP 0VT1tzIl9rm5fdPKbAvOw== X-UI-Out-Filterresults: notjunk:1; V01:K0:zHkcB8MayFw=:s5Q9Ky8/Mug6ia0qQ7r0f6 7zjKdHJa6Aue8T5G/RQqKTNvS3MP7u9b1TgBxE82uqJH/jF4hqaIP8S4lKlWZUIV0dvDPlC5b F1u4e9n9kDIUvEVL8Ln9cumAQJIsQL8OeBU6KdWQEgbmQYIukXi7aAFqOMEiBpetzB/P3V14X DUAa+zbWqcNMvwkKQta6CZFa3OsQU46tUzjzs/BMjgF8oMOdgtni29uDeZnhUhe82sQDKmFpQ u3lFMD/yOR/0LJdL31cpSjSV4t62X5VXEZ9EJqak8Rbx2V/1k9/e2IJJVw3+S9d/dWqr8Ltid tsrJ43kLquNDy+0QeCtohhMsYYZUkHMJtM+ssy7kWEdoUZxdMD+mSW3jZebGnVDp0f1lHTuqv c3N+7TqGpLo9cCkzh9njWCAI62PLBIhz+Kw23p+3wjE09joJ0DVLCkTAmPI5xpGY+OcgFpgZZ Xnr5vkdPfLRG9o9pHfFPE3Cag++ibIxGLBy1P9nHn8+eun36MX6Tl1mOf/pcU1EH/OQZZdP6w SaefgRNYtUWgAVGot3cOorWyGk0dVtUjBKKHwFt8eixyCuXj67/oLcE0j2eOat4BqbbWphWf/ /ISzXUq6q6NQkGuDTxu5JpWImaXsPZSghJTrfHyrJSP55VvueOs0TGXjK75ghC2MCWKOgsBTp JuwPOG5Ov7dYGBFfQEuk9UYIPhpXtbmwS2sRrxW+ty+hg052kKOjTf3zhdL4HpYKmuBw0YhUl B0gb78wiuvjVlm2b Sender: linux-parisc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM, RCVD_IN_DNSWL_HI,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PA8800 and PA8900 processors have a cache line length of 128 bytes. Reported-by: John David Anglin Signed-off-by: Helge Deller --- To unsubscribe from this list: send the line "unsubscribe linux-parisc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 47f11c7..a775f60 100644 --- a/arch/parisc/include/asm/cache.h +++ b/arch/parisc/include/asm/cache.h @@ -7,17 +7,19 @@ /* - * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have - * 32-byte cachelines. The default configuration is not for SMP anyway, - * so if you're building for SMP, you should select the appropriate - * processor type. There is a potential livelock danger when running - * a machine with this value set too small, but it's more probable you'll - * just ruin performance. + * Most PA 2.0 processors have 64-byte cachelines, but PA8800 and PA8900 + * processors have a cache line length of 128 bytes. + * PA 1.1 processors have 32-byte cachelines. + * There is a potential livelock danger when running a machine with this value + * set too small, but it's more probable you'll just ruin performance. */ -#ifdef CONFIG_PA20 +#if defined(CONFIG_PA8X00) +#define L1_CACHE_BYTES 128 +#define L1_CACHE_SHIFT 7 +#elif defined(CONFIG_PA20) #define L1_CACHE_BYTES 64 #define L1_CACHE_SHIFT 6 -#else +#else /* PA7XXX */ #define L1_CACHE_BYTES 32 #define L1_CACHE_SHIFT 5 #endif diff --git a/arch/parisc/include/asm/atomic.h b/arch/parisc/include/asm/atomic.h index 226f8ca9..b2bc4b7 100644 --- a/arch/parisc/include/asm/atomic.h +++ b/arch/parisc/include/asm/atomic.h @@ -19,14 +19,14 @@ #ifdef CONFIG_SMP #include -#include /* we use L1_CACHE_BYTES */ +#include /* we use L1_CACHE_SHIFT */ /* Use an array of spinlocks for our atomic_ts. * Hash function to index into a different SPINLOCK. * Since "a" is usually an address, use one spinlock per cacheline. */ # define ATOMIC_HASH_SIZE 4 -# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) (a))/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) +# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) (a)) >> L1_CACHE_SHIFT) & (ATOMIC_HASH_SIZE-1) ])) extern arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;