[1/2] drm/i915: Don't bypass LRC on CHV
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Message ID 1441724745-10515-1-git-send-email-ville.syrjala@linux.intel.com
State New
Headers show

Commit Message

Ville Syrjälä Sept. 8, 2015, 3:05 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The docs are unclear as usual, so it's not clear whether LRC should be
bypassed, performed normally or GRC code should be used as the LRC code.
Some old docs stated that LRC bypass ought to be used, more recent ones
no longer say that. Some docs indicated that we could use GRC as the LRC
code on CHV, but the BIOS doesn't do that, so let's not do it either.

Besides to enable LRC bypass properly, I believe we should set the bit
already before deasserting cmnreset.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 5 -----
 drivers/gpu/drm/i915/intel_hdmi.c | 5 -----
 2 files changed, 10 deletions(-)

Comments

deepak.s@linux.intel.com Oct. 5, 2015, 10:25 a.m. UTC | #1
On Tuesday 08 September 2015 08:35 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The docs are unclear as usual, so it's not clear whether LRC should be
> bypassed, performed normally or GRC code should be used as the LRC code.
> Some old docs stated that LRC bypass ought to be used, more recent ones
> no longer say that. Some docs indicated that we could use GRC as the LRC
> code on CHV, but the BIOS doesn't do that, so let's not do it either.
>
> Besides to enable LRC bypass properly, I believe we should set the bit
> already before deasserting cmnreset.

Can we add a Log to indicate what BIOS is configuring? I think it helps in debugging?


Change looks fine.
Reviewed-by: Deepak S<deepak.s@linux.intel.com>


> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c   | 5 -----
>   drivers/gpu/drm/i915/intel_hdmi.c | 5 -----
>   2 files changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 45ab25e..825d5ab 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3416,11 +3416,6 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
>   		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>   	}
>   
> -	/* LRC Bypass */
> -	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> -	val |= DPIO_LRC_BYPASS;
> -	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
> -
>   	mutex_unlock(&dev_priv->sb_lock);
>   
>   	return 0;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index feb31d8..9d7923d 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1941,11 +1941,6 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
>   	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
>   	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
>   
> -	/* LRC Bypass */
> -	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> -	val |= DPIO_LRC_BYPASS;
> -	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
> -
>   	mutex_unlock(&dev_priv->sb_lock);
>   
>   	intel_hdmi->set_infoframes(&encoder->base,

Patch
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diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 45ab25e..825d5ab 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3416,11 +3416,6 @@  static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
 	}
 
-	/* LRC Bypass */
-	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
-	val |= DPIO_LRC_BYPASS;
-	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
-
 	mutex_unlock(&dev_priv->sb_lock);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index feb31d8..9d7923d 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1941,11 +1941,6 @@  static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
 	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
 
-	/* LRC Bypass */
-	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
-	val |= DPIO_LRC_BYPASS;
-	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
-
 	mutex_unlock(&dev_priv->sb_lock);
 
 	intel_hdmi->set_infoframes(&encoder->base,