| Message ID | 1442341820-23531-1-git-send-email-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index fe06accb0..3f18ea1 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2465,6 +2465,16 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx, return -ENOMEM; } + if (!(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) { + ret = i915_gem_object_set_cache_level(ctx_obj, + I915_CACHE_LLC); + if (ret) { + DRM_ERROR("set cache level for context failed: %d\n", + ret); + goto error_deref_obj; + } + } + ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE); if (IS_ERR(ringbuf)) { ret = PTR_ERR(ringbuf);
The context object on all execlist platforms is mapped to the GPU with a CPU-GPU cache coherent mapping. This matched the default cache level on LLC platforms, but not on CHV. Set the cache level explicitly to fix this up. On BXT A stepping the coherency is not guaranteed due to a HW issue, to work around this we treat the mapping as not coherent. Atm this change is only for consistency, it doesn't affect anything in practice, but the following patch will depend on it to do a CLFLUSH only on non-coherent platforms. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 10 ++++++++++ 1 file changed, 10 insertions(+)