@@ -1337,11 +1337,10 @@ static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
}
}
-static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
+static int map_cpu(drm_intel_bo *bo)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
- struct drm_i915_gem_set_domain set_domain;
int ret;
if (bo_gem->is_userptr) {
@@ -1350,8 +1349,6 @@ static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
return 0;
}
- pthread_mutex_lock(&bufmgr_gem->lock);
-
if (bo_gem->map_count++ == 0)
drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem);
@@ -1384,6 +1381,24 @@ static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
bo_gem->mem_virtual);
bo->virtual = bo_gem->mem_virtual;
+ return 0;
+}
+
+static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
+{
+ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
+ drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
+ struct drm_i915_gem_set_domain set_domain;
+ int ret;
+
+ pthread_mutex_lock(&bufmgr_gem->lock);
+
+ ret = map_cpu(bo);
+ if (ret || bo_gem->is_userptr) {
+ pthread_mutex_unlock(&bufmgr_gem->lock);
+ return ret;
+ }
+
memclear(set_domain);
set_domain.handle = bo_gem->gem_handle;
set_domain.read_domains = I915_GEM_DOMAIN_CPU;
@@ -1536,9 +1551,7 @@ int
drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
-#ifdef HAVE_VALGRIND
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
-#endif
int ret;
/* If the CPU cache isn't coherent with the GTT, then use a
@@ -1553,7 +1566,10 @@ drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
pthread_mutex_lock(&bufmgr_gem->lock);
- ret = map_gtt(bo);
+ if (bo_gem->tiling_mode == I915_TILING_NONE)
+ ret = map_cpu(bo);
+ else
+ ret = map_gtt(bo);
if (ret == 0) {
drm_intel_gem_bo_mark_mmaps_incoherent(bo);
VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));