[04/43] drm/i915: Parametrize fence registers
diff mbox

Message ID 1442595836-23981-5-git-send-email-ville.syrjala@linux.intel.com
State New
Headers show

Commit Message

Ville Syrjälä Sept. 18, 2015, 5:03 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_fence.c | 42 +++++++++++++++++------------------
 drivers/gpu/drm/i915/i915_gpu_error.c | 21 ++++++++----------
 drivers/gpu/drm/i915/i915_reg.h       | 12 +++++-----
 3 files changed, 37 insertions(+), 38 deletions(-)

Comments

Jani Nikula Sept. 21, 2015, 7:45 a.m. UTC | #1
On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_fence.c | 42 +++++++++++++++++------------------
>  drivers/gpu/drm/i915/i915_gpu_error.c | 21 ++++++++----------
>  drivers/gpu/drm/i915/i915_reg.h       | 12 +++++-----
>  3 files changed, 37 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
> index 6077dff..ff94560 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -59,19 +59,19 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
>  				 struct drm_i915_gem_object *obj)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int fence_reg;
> +	int fence_reg_lo, fence_reg_hi;
>  	int fence_pitch_shift;
>  
>  	if (INTEL_INFO(dev)->gen >= 6) {
> -		fence_reg = FENCE_REG_SANDYBRIDGE_0;
> -		fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
> +		fence_reg_lo = FENCE_REG_GEN6_LO(reg);
> +		fence_reg_hi = FENCE_REG_GEN6_HI(reg);
> +		fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
>  	} else {
> -		fence_reg = FENCE_REG_965_0;
> +		fence_reg_lo = FENCE_REG_965_LO(reg);
> +		fence_reg_hi = FENCE_REG_965_HI(reg);
>  		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
>  	}
>  
> -	fence_reg += reg * 8;
> -
>  	/* To w/a incoherency with non-atomic 64-bit register updates,
>  	 * we split the 64-bit update into two 32-bit writes. In order
>  	 * for a partial fence not to be evaluated between writes, we
> @@ -81,8 +81,8 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
>  	 * For extra levels of paranoia, we make sure each step lands
>  	 * before applying the next step.
>  	 */
> -	I915_WRITE(fence_reg, 0);
> -	POSTING_READ(fence_reg);
> +	I915_WRITE(fence_reg_lo, 0);
> +	POSTING_READ(fence_reg_lo);
>  
>  	if (obj) {
>  		u32 size = i915_gem_obj_ggtt_size(obj);
> @@ -103,14 +103,14 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg,
>  			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
>  		val |= I965_FENCE_REG_VALID;
>  
> -		I915_WRITE(fence_reg + 4, val >> 32);
> -		POSTING_READ(fence_reg + 4);
> +		I915_WRITE(fence_reg_hi, val >> 32);
> +		POSTING_READ(fence_reg_hi);
>  
> -		I915_WRITE(fence_reg + 0, val);
> -		POSTING_READ(fence_reg);
> +		I915_WRITE(fence_reg_lo, val);
> +		POSTING_READ(fence_reg_lo);
>  	} else {
> -		I915_WRITE(fence_reg + 4, 0);
> -		POSTING_READ(fence_reg + 4);
> +		I915_WRITE(fence_reg_hi, 0);
> +		POSTING_READ(fence_reg_hi);
>  	}
>  }
>  
> @@ -118,7 +118,7 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
>  				 struct drm_i915_gem_object *obj)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 val;
> +	u32 fence_reg, val;
>  
>  	if (obj) {
>  		u32 size = i915_gem_obj_ggtt_size(obj);
> @@ -150,12 +150,12 @@ static void i915_write_fence_reg(struct drm_device *dev, int reg,
>  		val = 0;
>  
>  	if (reg < 8)
> -		reg = FENCE_REG_830_0 + reg * 4;
> +		fence_reg = FENCE_REG_830(reg);
>  	else
> -		reg = FENCE_REG_945_8 + (reg - 8) * 4;
> +		fence_reg = FENCE_REG_945_8(reg);
>  
> -	I915_WRITE(reg, val);
> -	POSTING_READ(reg);
> +	I915_WRITE(fence_reg, val);
> +	POSTING_READ(fence_reg);
>  }
>  
>  static void i830_write_fence_reg(struct drm_device *dev, int reg,
> @@ -186,8 +186,8 @@ static void i830_write_fence_reg(struct drm_device *dev, int reg,
>  	} else
>  		val = 0;
>  
> -	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
> -	POSTING_READ(FENCE_REG_830_0 + reg * 4);
> +	I915_WRITE(FENCE_REG_830(reg), val);
> +	POSTING_READ(FENCE_REG_830(reg));
>  }
>  
>  inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 3379f9c..e873eb4 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -787,19 +787,16 @@ static void i915_gem_record_fences(struct drm_device *dev,
>  
>  	if (IS_GEN3(dev) || IS_GEN2(dev)) {
>  		for (i = 0; i < 8; i++)
> -			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
> -		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> -			for (i = 0; i < 8; i++)
> -				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
> -							      (i * 4));
> -	} else if (IS_GEN5(dev) || IS_GEN4(dev))
> -		for (i = 0; i < 16; i++)
> -			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
> -						      (i * 8));
> -	else if (INTEL_INFO(dev)->gen >= 6)
> +			error->fence[i] = I915_READ(FENCE_REG_830(i));
> +		for (i = 8; i < dev_priv->num_fence_regs; i++)
> +			error->fence[i] = I915_READ(FENCE_REG_945_8(i));
> +	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
>  		for (i = 0; i < dev_priv->num_fence_regs; i++)
> -			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
> -						      (i * 8));
> +			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
> +	} else if (INTEL_INFO(dev)->gen >= 6) {
> +		for (i = 0; i < dev_priv->num_fence_regs; i++)
> +			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> +	}
>  }
>  
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 44cedbf..b1cf17a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1437,8 +1437,8 @@ enum skl_disp_power_wells {
>  /*
>   * Fence registers
>   */
> -#define FENCE_REG_830_0			0x2000
> -#define FENCE_REG_945_8			0x3000
> +#define FENCE_REG_830(i)		(0x2000 + (i) * 4) /* 8 registers */
> +#define FENCE_REG_945_8(i)		(0x3000 + ((i) - 8) * 4) /* 8 registers */

How about defining that as

#define FENCE_REG_945(i) (i < 8 ? FENCE_REG_830(i) : (0x3000 + ((i) - 8) * 4))

and changing the code to look at platforms, not reg number?


BR,
Jani.


>  #define   I830_FENCE_START_MASK		0x07f80000
>  #define   I830_FENCE_TILING_Y_SHIFT	12
>  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
> @@ -1451,14 +1451,16 @@ enum skl_disp_power_wells {
>  #define   I915_FENCE_START_MASK		0x0ff00000
>  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
>  
> -#define FENCE_REG_965_0			0x03000
> +#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
> +#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
>  #define   I965_FENCE_PITCH_SHIFT	2
>  #define   I965_FENCE_TILING_Y_SHIFT	1
>  #define   I965_FENCE_REG_VALID		(1<<0)
>  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
>  
> -#define FENCE_REG_SANDYBRIDGE_0		0x100000
> -#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
> +#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
> +#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
> +#define   GEN6_FENCE_PITCH_SHIFT	32
>  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
>  
>  
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Ville Syrjälä Sept. 21, 2015, 12:33 p.m. UTC | #2
On Mon, Sep 21, 2015 at 10:45:46AM +0300, Jani Nikula wrote:
> On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_gem_fence.c | 42 +++++++++++++++++------------------
> >  drivers/gpu/drm/i915/i915_gpu_error.c | 21 ++++++++----------
> >  drivers/gpu/drm/i915/i915_reg.h       | 12 +++++-----
> >  3 files changed, 37 insertions(+), 38 deletions(-)
> >
<snip>
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index 3379f9c..e873eb4 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -787,19 +787,16 @@ static void i915_gem_record_fences(struct drm_device *dev,
> >  
> >  	if (IS_GEN3(dev) || IS_GEN2(dev)) {
> >  		for (i = 0; i < 8; i++)
> > -			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
> > -		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> > -			for (i = 0; i < 8; i++)
> > -				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
> > -							      (i * 4));
> > -	} else if (IS_GEN5(dev) || IS_GEN4(dev))
> > -		for (i = 0; i < 16; i++)
> > -			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
> > -						      (i * 8));
> > -	else if (INTEL_INFO(dev)->gen >= 6)
> > +			error->fence[i] = I915_READ(FENCE_REG_830(i));
> > +		for (i = 8; i < dev_priv->num_fence_regs; i++)
> > +			error->fence[i] = I915_READ(FENCE_REG_945_8(i));
> > +	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
> >  		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > -			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
> > -						      (i * 8));
> > +			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
> > +	} else if (INTEL_INFO(dev)->gen >= 6) {
> > +		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > +			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> > +	}
> >  }
> >  
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 44cedbf..b1cf17a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1437,8 +1437,8 @@ enum skl_disp_power_wells {
> >  /*
> >   * Fence registers
> >   */
> > -#define FENCE_REG_830_0			0x2000
> > -#define FENCE_REG_945_8			0x3000
> > +#define FENCE_REG_830(i)		(0x2000 + (i) * 4) /* 8 registers */
> > +#define FENCE_REG_945_8(i)		(0x3000 + ((i) - 8) * 4) /* 8 registers */
> 
> How about defining that as
> 
> #define FENCE_REG_945(i) (i < 8 ? FENCE_REG_830(i) : (0x3000 + ((i) - 8) * 4))
> 
> and changing the code to look at platforms, not reg number?

Yeah, I guess we can hide the magic entirely. In fact we wouldn't even
need any gen2 vs. gen3 platforms checks anymore with that macro.

> 
> 
> BR,
> Jani.
> 
> 
> >  #define   I830_FENCE_START_MASK		0x07f80000
> >  #define   I830_FENCE_TILING_Y_SHIFT	12
> >  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
> > @@ -1451,14 +1451,16 @@ enum skl_disp_power_wells {
> >  #define   I915_FENCE_START_MASK		0x0ff00000
> >  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
> >  
> > -#define FENCE_REG_965_0			0x03000
> > +#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
> > +#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
> >  #define   I965_FENCE_PITCH_SHIFT	2
> >  #define   I965_FENCE_TILING_Y_SHIFT	1
> >  #define   I965_FENCE_REG_VALID		(1<<0)
> >  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
> >  
> > -#define FENCE_REG_SANDYBRIDGE_0		0x100000
> > -#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
> > +#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
> > +#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
> > +#define   GEN6_FENCE_PITCH_SHIFT	32
> >  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
> >  
> >  
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
Ville Syrjälä Sept. 21, 2015, 1:07 p.m. UTC | #3
On Mon, Sep 21, 2015 at 03:33:00PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 21, 2015 at 10:45:46AM +0300, Jani Nikula wrote:
> > On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_gem_fence.c | 42 +++++++++++++++++------------------
> > >  drivers/gpu/drm/i915/i915_gpu_error.c | 21 ++++++++----------
> > >  drivers/gpu/drm/i915/i915_reg.h       | 12 +++++-----
> > >  3 files changed, 37 insertions(+), 38 deletions(-)
> > >
> <snip>
> > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> > > index 3379f9c..e873eb4 100644
> > > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > > @@ -787,19 +787,16 @@ static void i915_gem_record_fences(struct drm_device *dev,
> > >  
> > >  	if (IS_GEN3(dev) || IS_GEN2(dev)) {
> > >  		for (i = 0; i < 8; i++)
> > > -			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
> > > -		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> > > -			for (i = 0; i < 8; i++)
> > > -				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
> > > -							      (i * 4));
> > > -	} else if (IS_GEN5(dev) || IS_GEN4(dev))
> > > -		for (i = 0; i < 16; i++)
> > > -			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
> > > -						      (i * 8));
> > > -	else if (INTEL_INFO(dev)->gen >= 6)
> > > +			error->fence[i] = I915_READ(FENCE_REG_830(i));
> > > +		for (i = 8; i < dev_priv->num_fence_regs; i++)
> > > +			error->fence[i] = I915_READ(FENCE_REG_945_8(i));
> > > +	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
> > >  		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > > -			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
> > > -						      (i * 8));
> > > +			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
> > > +	} else if (INTEL_INFO(dev)->gen >= 6) {
> > > +		for (i = 0; i < dev_priv->num_fence_regs; i++)
> > > +			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> > > +	}
> > >  }
> > >  
> > >  
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 44cedbf..b1cf17a 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1437,8 +1437,8 @@ enum skl_disp_power_wells {
> > >  /*
> > >   * Fence registers
> > >   */
> > > -#define FENCE_REG_830_0			0x2000
> > > -#define FENCE_REG_945_8			0x3000
> > > +#define FENCE_REG_830(i)		(0x2000 + (i) * 4) /* 8 registers */
> > > +#define FENCE_REG_945_8(i)		(0x3000 + ((i) - 8) * 4) /* 8 registers */
> > 
> > How about defining that as
> > 
> > #define FENCE_REG_945(i) (i < 8 ? FENCE_REG_830(i) : (0x3000 + ((i) - 8) * 4))
> > 
> > and changing the code to look at platforms, not reg number?
> 
> Yeah, I guess we can hide the magic entirely. In fact we wouldn't even
> need any gen2 vs. gen3 platforms checks anymore with that macro.

Oh I think I already considered making this even more magic with
something like this:
(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
or
(0x2000 + (((i) >> 3) * 0x1000) + ((i) & 7) * 4)

Not sure if that's too obscure for people? I suppose I could toss in a
comment in there to explain it a bit.

> 
> > 
> > 
> > BR,
> > Jani.
> > 
> > 
> > >  #define   I830_FENCE_START_MASK		0x07f80000
> > >  #define   I830_FENCE_TILING_Y_SHIFT	12
> > >  #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
> > > @@ -1451,14 +1451,16 @@ enum skl_disp_power_wells {
> > >  #define   I915_FENCE_START_MASK		0x0ff00000
> > >  #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
> > >  
> > > -#define FENCE_REG_965_0			0x03000
> > > +#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
> > > +#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
> > >  #define   I965_FENCE_PITCH_SHIFT	2
> > >  #define   I965_FENCE_TILING_Y_SHIFT	1
> > >  #define   I965_FENCE_REG_VALID		(1<<0)
> > >  #define   I965_FENCE_MAX_PITCH_VAL	0x0400
> > >  
> > > -#define FENCE_REG_SANDYBRIDGE_0		0x100000
> > > -#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
> > > +#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
> > > +#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
> > > +#define   GEN6_FENCE_PITCH_SHIFT	32
> > >  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
> > >  
> > >  
> > > -- 
> > > 2.4.6
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Jani Nikula, Intel Open Source Technology Center
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
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Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 6077dff..ff94560 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -59,19 +59,19 @@  static void i965_write_fence_reg(struct drm_device *dev, int reg,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int fence_reg;
+	int fence_reg_lo, fence_reg_hi;
 	int fence_pitch_shift;
 
 	if (INTEL_INFO(dev)->gen >= 6) {
-		fence_reg = FENCE_REG_SANDYBRIDGE_0;
-		fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
+		fence_reg_lo = FENCE_REG_GEN6_LO(reg);
+		fence_reg_hi = FENCE_REG_GEN6_HI(reg);
+		fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
 	} else {
-		fence_reg = FENCE_REG_965_0;
+		fence_reg_lo = FENCE_REG_965_LO(reg);
+		fence_reg_hi = FENCE_REG_965_HI(reg);
 		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
 	}
 
-	fence_reg += reg * 8;
-
 	/* To w/a incoherency with non-atomic 64-bit register updates,
 	 * we split the 64-bit update into two 32-bit writes. In order
 	 * for a partial fence not to be evaluated between writes, we
@@ -81,8 +81,8 @@  static void i965_write_fence_reg(struct drm_device *dev, int reg,
 	 * For extra levels of paranoia, we make sure each step lands
 	 * before applying the next step.
 	 */
-	I915_WRITE(fence_reg, 0);
-	POSTING_READ(fence_reg);
+	I915_WRITE(fence_reg_lo, 0);
+	POSTING_READ(fence_reg_lo);
 
 	if (obj) {
 		u32 size = i915_gem_obj_ggtt_size(obj);
@@ -103,14 +103,14 @@  static void i965_write_fence_reg(struct drm_device *dev, int reg,
 			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
 		val |= I965_FENCE_REG_VALID;
 
-		I915_WRITE(fence_reg + 4, val >> 32);
-		POSTING_READ(fence_reg + 4);
+		I915_WRITE(fence_reg_hi, val >> 32);
+		POSTING_READ(fence_reg_hi);
 
-		I915_WRITE(fence_reg + 0, val);
-		POSTING_READ(fence_reg);
+		I915_WRITE(fence_reg_lo, val);
+		POSTING_READ(fence_reg_lo);
 	} else {
-		I915_WRITE(fence_reg + 4, 0);
-		POSTING_READ(fence_reg + 4);
+		I915_WRITE(fence_reg_hi, 0);
+		POSTING_READ(fence_reg_hi);
 	}
 }
 
@@ -118,7 +118,7 @@  static void i915_write_fence_reg(struct drm_device *dev, int reg,
 				 struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 val;
+	u32 fence_reg, val;
 
 	if (obj) {
 		u32 size = i915_gem_obj_ggtt_size(obj);
@@ -150,12 +150,12 @@  static void i915_write_fence_reg(struct drm_device *dev, int reg,
 		val = 0;
 
 	if (reg < 8)
-		reg = FENCE_REG_830_0 + reg * 4;
+		fence_reg = FENCE_REG_830(reg);
 	else
-		reg = FENCE_REG_945_8 + (reg - 8) * 4;
+		fence_reg = FENCE_REG_945_8(reg);
 
-	I915_WRITE(reg, val);
-	POSTING_READ(reg);
+	I915_WRITE(fence_reg, val);
+	POSTING_READ(fence_reg);
 }
 
 static void i830_write_fence_reg(struct drm_device *dev, int reg,
@@ -186,8 +186,8 @@  static void i830_write_fence_reg(struct drm_device *dev, int reg,
 	} else
 		val = 0;
 
-	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
-	POSTING_READ(FENCE_REG_830_0 + reg * 4);
+	I915_WRITE(FENCE_REG_830(reg), val);
+	POSTING_READ(FENCE_REG_830(reg));
 }
 
 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3379f9c..e873eb4 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -787,19 +787,16 @@  static void i915_gem_record_fences(struct drm_device *dev,
 
 	if (IS_GEN3(dev) || IS_GEN2(dev)) {
 		for (i = 0; i < 8; i++)
-			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
-		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-			for (i = 0; i < 8; i++)
-				error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
-							      (i * 4));
-	} else if (IS_GEN5(dev) || IS_GEN4(dev))
-		for (i = 0; i < 16; i++)
-			error->fence[i] = I915_READ64(FENCE_REG_965_0 +
-						      (i * 8));
-	else if (INTEL_INFO(dev)->gen >= 6)
+			error->fence[i] = I915_READ(FENCE_REG_830(i));
+		for (i = 8; i < dev_priv->num_fence_regs; i++)
+			error->fence[i] = I915_READ(FENCE_REG_945_8(i));
+	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
-			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
-						      (i * 8));
+			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
+	} else if (INTEL_INFO(dev)->gen >= 6) {
+		for (i = 0; i < dev_priv->num_fence_regs; i++)
+			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
+	}
 }
 
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44cedbf..b1cf17a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1437,8 +1437,8 @@  enum skl_disp_power_wells {
 /*
  * Fence registers
  */
-#define FENCE_REG_830_0			0x2000
-#define FENCE_REG_945_8			0x3000
+#define FENCE_REG_830(i)		(0x2000 + (i) * 4) /* 8 registers */
+#define FENCE_REG_945_8(i)		(0x3000 + ((i) - 8) * 4) /* 8 registers */
 #define   I830_FENCE_START_MASK		0x07f80000
 #define   I830_FENCE_TILING_Y_SHIFT	12
 #define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
@@ -1451,14 +1451,16 @@  enum skl_disp_power_wells {
 #define   I915_FENCE_START_MASK		0x0ff00000
 #define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
 
-#define FENCE_REG_965_0			0x03000
+#define FENCE_REG_965_LO(i)		(0x03000 + (i) * 8)
+#define FENCE_REG_965_HI(i)		(0x03000 + (i) * 8 + 4)
 #define   I965_FENCE_PITCH_SHIFT	2
 #define   I965_FENCE_TILING_Y_SHIFT	1
 #define   I965_FENCE_REG_VALID		(1<<0)
 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
 
-#define FENCE_REG_SANDYBRIDGE_0		0x100000
-#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
+#define FENCE_REG_GEN6_LO(i)	(0x100000 + (i) * 8)
+#define FENCE_REG_GEN6_HI(i)	(0x100000 + (i) * 8 + 4)
+#define   GEN6_FENCE_PITCH_SHIFT	32
 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800