[12/43] drm/i915: Add LO/HI PRIVATE_PAT registers
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Message ID 1442595836-23981-13-git-send-email-ville.syrjala@linux.intel.com
State New
Headers show

Commit Message

Ville Syrjälä Sept. 18, 2015, 5:03 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
 drivers/gpu/drm/i915/i915_reg.h     | 3 ++-
 2 files changed, 6 insertions(+), 5 deletions(-)

Comments

Jani Nikula Sept. 28, 2015, 11:40 a.m. UTC | #1
On Fri, 18 Sep 2015, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
>  drivers/gpu/drm/i915/i915_reg.h     | 3 ++-
>  2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 8786281..2b6dd70 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2879,8 +2879,8 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
>  
>  	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
>  	 * write would work. */
> -	I915_WRITE(GEN8_PRIVATE_PAT, pat);
> -	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
> +	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
> +	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
>  }
>  
>  static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
> @@ -2914,8 +2914,8 @@ static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
>  	      GEN8_PPAT(6, CHV_PPAT_SNOOP) |
>  	      GEN8_PPAT(7, CHV_PPAT_SNOOP);
>  
> -	I915_WRITE(GEN8_PRIVATE_PAT, pat);
> -	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
> +	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
> +	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
>  }
>  
>  static int gen8_gmch_probe(struct drm_device *dev,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 61414c8..a04fa2a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1544,7 +1544,8 @@ enum skl_disp_power_wells {
>  #define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
>  #define   RING_FAULT_VALID	(1<<0)
>  #define DONE_REG		0x40b0
> -#define GEN8_PRIVATE_PAT	0x40e0
> +#define GEN8_PRIVATE_PAT_LO	0x40e0
> +#define GEN8_PRIVATE_PAT_HI	(0x40e0 + 4)
>  #define BSD_HWS_PGA_GEN7	(0x04180)
>  #define BLT_HWS_PGA_GEN7	(0x04280)
>  #define VEBOX_HWS_PGA_GEN7	(0x04380)
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch
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diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8786281..2b6dd70 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2879,8 +2879,8 @@  static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
 
 	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
 	 * write would work. */
-	I915_WRITE(GEN8_PRIVATE_PAT, pat);
-	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
+	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
 }
 
 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
@@ -2914,8 +2914,8 @@  static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
 	      GEN8_PPAT(6, CHV_PPAT_SNOOP) |
 	      GEN8_PPAT(7, CHV_PPAT_SNOOP);
 
-	I915_WRITE(GEN8_PRIVATE_PAT, pat);
-	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
+	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
+	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
 }
 
 static int gen8_gmch_probe(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 61414c8..a04fa2a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1544,7 +1544,8 @@  enum skl_disp_power_wells {
 #define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
 #define   RING_FAULT_VALID	(1<<0)
 #define DONE_REG		0x40b0
-#define GEN8_PRIVATE_PAT	0x40e0
+#define GEN8_PRIVATE_PAT_LO	0x40e0
+#define GEN8_PRIVATE_PAT_HI	(0x40e0 + 4)
 #define BSD_HWS_PGA_GEN7	(0x04180)
 #define BLT_HWS_PGA_GEN7	(0x04280)
 #define VEBOX_HWS_PGA_GEN7	(0x04380)