diff mbox

[28/43] drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function

Message ID 1442595836-23981-29-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä Sept. 18, 2015, 5:03 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++--------------
 1 file changed, 17 insertions(+), 14 deletions(-)

Comments

Jesse Barnes Oct. 12, 2015, 4:05 p.m. UTC | #1 
On 09/18/2015 10:03 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++--------------
>  1 file changed, 17 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 16948b2..24f68de 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -139,27 +139,30 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
>  /*
>   * We should clear IMR at preinstall/uninstall, and just check at postinstall.
>   */
> -#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
> -	u32 val = I915_READ(reg); \
> -	if (val) { \
> -		WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
> -		     (reg), val); \
> -		I915_WRITE((reg), 0xffffffff); \
> -		POSTING_READ(reg); \
> -		I915_WRITE((reg), 0xffffffff); \
> -		POSTING_READ(reg); \
> -	} \
> -} while (0)
> +static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
> +{
> +	u32 val = I915_READ(reg);
> +
> +	if (val == 0)
> +		return;
> +
> +	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
> +	     reg, val);
> +	I915_WRITE(reg, 0xffffffff);
> +	POSTING_READ(reg);
> +	I915_WRITE(reg, 0xffffffff);
> +	POSTING_READ(reg);
> +}
>  
>  #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
> -	GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
> +	gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
>  	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
>  	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
>  	POSTING_READ(GEN8_##type##_IMR(which)); \
>  } while (0)
>  
>  #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
> -	GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
> +	gen5_assert_iir_is_zero(dev_priv, type##IIR); \
>  	I915_WRITE(type##IER, (ier_val)); \
>  	I915_WRITE(type##IMR, (imr_val)); \
>  	POSTING_READ(type##IMR); \
> @@ -3276,7 +3279,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
>  	else
>  		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
>  
> -	GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
> +	gen5_assert_iir_is_zero(dev_priv, SDEIIR);
>  	I915_WRITE(SDEIMR, ~mask);
>  }
>  
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 16948b2..24f68de 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -139,27 +139,30 @@  static const u32 hpd_bxt[HPD_NUM_PINS] = {
 /*
  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
  */
-#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
-	u32 val = I915_READ(reg); \
-	if (val) { \
-		WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
-		     (reg), val); \
-		I915_WRITE((reg), 0xffffffff); \
-		POSTING_READ(reg); \
-		I915_WRITE((reg), 0xffffffff); \
-		POSTING_READ(reg); \
-	} \
-} while (0)
+static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 reg)
+{
+	u32 val = I915_READ(reg);
+
+	if (val == 0)
+		return;
+
+	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
+	     reg, val);
+	I915_WRITE(reg, 0xffffffff);
+	POSTING_READ(reg);
+	I915_WRITE(reg, 0xffffffff);
+	POSTING_READ(reg);
+}
 
 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
-	GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
+	gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 	POSTING_READ(GEN8_##type##_IMR(which)); \
 } while (0)
 
 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
-	GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
+	gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 	I915_WRITE(type##IER, (ier_val)); \
 	I915_WRITE(type##IMR, (imr_val)); \
 	POSTING_READ(type##IMR); \
@@ -3276,7 +3279,7 @@  static void ibx_irq_postinstall(struct drm_device *dev)
 	else
 		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
 
-	GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
+	gen5_assert_iir_is_zero(dev_priv, SDEIIR);
 	I915_WRITE(SDEIMR, ~mask);
 }