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[2/2] Documentation: DT bindings: rockchip-i2s: add capture and lrck-mode

Message ID 1442979683-9441-3-git-send-email-sugar.zhang@rock-chips.com (mailing list archive)
State New, archived
Headers show

Commit Message

Sugar Zhang Sept. 23, 2015, 3:41 a.m. UTC
rockchip,capture-channels: max capture channels, 2 channels default.
rockchip,lrck-mode: 0: rxtx separate, 1: tx share, 2: rx share.
default use 'rxtx separate' mode.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
---
 Documentation/devicetree/bindings/sound/rockchip-i2s.txt | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Mark Brown Sept. 23, 2015, 4:20 p.m. UTC | #1
On Wed, Sep 23, 2015 at 11:41:23AM +0800, Sugar Zhang wrote:

> rockchip,lrck-mode: 0: rxtx separate, 1: tx share, 2: rx share.
> default use 'rxtx separate' mode.

I'm slightly confused about this property - is this covering differences
in the IP deployed on different SoCs or is it covering how the SoC is
wired into the board?  If it's for how the SoC is wired into the board
(ie, Rx and Tx wired together) then this should already be covered by
either the machine driver or the device at the other end of the link.
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Patch

diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt
index 9b82c20..4066b85 100644
--- a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt
@@ -21,6 +21,9 @@  Required properties:
 - clock-names: should contain followings:
    - "i2s_hclk": clock for I2S BUS
    - "i2s_clk" : clock for I2S controller
+- rockchip,capture-channels: max capture channels, if not set, 2 channels default.
+- rockchip,lrck-mode: select lrck use mode: 0: rxtx separate, 1: tx share, 2: rx share.
+  default use 'rxtx seprate' mode.
 
 Example for rk3288 I2S controller:
 
@@ -34,4 +37,6 @@  i2s@ff890000 {
 	dma-names = "tx", "rx";
 	clock-names = "i2s_hclk", "i2s_clk";
 	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
+	rockchip,capture-channels = <2>;
+	rockchip,lrck-mode = <0>;
 };