From patchwork Sun Sep 27 16:07:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 7273391 Return-Path: X-Original-To: patchwork-linux-parisc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D4AC4BEEA4 for ; Sun, 27 Sep 2015 16:07:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8326520841 for ; Sun, 27 Sep 2015 16:07:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2F23F2083F for ; Sun, 27 Sep 2015 16:07:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756283AbbI0QHE (ORCPT ); Sun, 27 Sep 2015 12:07:04 -0400 Received: from simcoe207srvr.owm.bell.net ([184.150.200.207]:47809 "EHLO torfep01.bell.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1756221AbbI0QHD (ORCPT ); Sun, 27 Sep 2015 12:07:03 -0400 Received: from bell.net torfep01 184.150.200.158 by torfep01.bell.net with ESMTP id <20150927160701.KPSV22640.torfep01.bell.net@torspm01.bell.net> for ; Sun, 27 Sep 2015 12:07:01 -0400 Received: from [192.168.2.10] (really [76.69.120.10]) by torspm01.bell.net with ESMTP id <20150927160701.WFDV24849.torspm01.bell.net@[192.168.2.10]>; Sun, 27 Sep 2015 12:07:01 -0400 Subject: [PATCH v2][RFC] parisc: Change L1_CACHE_BYTES to 16 Mime-Version: 1.0 (Apple Message framework v1085) From: John David Anglin In-Reply-To: <42430464-867C-4E0B-8E95-C6CDB6D8A0B2@bell.net> Date: Sun, 27 Sep 2015 12:07:00 -0400 Cc: linux-parisc List , Helge Deller , James Bottomley Message-Id: <32A3BF6F-B243-4AD4-9AE9-A5F9DAE0270A@bell.net> References: <42430464-867C-4E0B-8E95-C6CDB6D8A0B2@bell.net> To: John David Anglin X-Mailer: Apple Mail (2.1085) X-Opwv-CommTouchExtSvcRefID: str=0001.0A020202.56081425.0066, ss=1, re=0.000, fgs=0 Sender: linux-parisc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, T_TVD_MIME_EPI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 2015-09-26, at 11:38 AM, John David Anglin wrote: > The attached change reduces L1_CACHE_BYTES from 32 on PA1.1 and 64 on PA2.0 to 16. > > This is based on examination of the L1 cache design for the PA-8700 processor where it can > be seen the processor loads two double words per cycle. This line length is consistent with the > original alignment requirement for the ldcw instruction. > > Thus, we need to distinguish between the L1 and L2 (SMP) cache line lengths. > > The attached change bumps SMP_CACHE_BYTES to 128 bytes as this is the line length used > on PA-8800 and PA-8900 processors. This increases the overall kernel size somewhat but seems > logically correct. Slight tweak to previous. This version only bumps SMP_CACHE_BYTES when CONFIG_SMP is defined. Signed-off-by: John David Anglin --- John David Anglin dave.anglin@bell.net diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 47f11c7..cf11dd4 100644 --- a/arch/parisc/include/asm/cache.h +++ b/arch/parisc/include/asm/cache.h @@ -7,24 +7,27 @@ /* - * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have - * 32-byte cachelines. The default configuration is not for SMP anyway, + * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors + * have 32-byte cachelines. The default configuration is not for SMP anyway, * so if you're building for SMP, you should select the appropriate * processor type. There is a potential livelock danger when running * a machine with this value set too small, but it's more probable you'll * just ruin performance. */ -#ifdef CONFIG_PA20 -#define L1_CACHE_BYTES 64 -#define L1_CACHE_SHIFT 6 -#else -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 -#endif +#define L1_CACHE_BYTES 16 +#define L1_CACHE_SHIFT 4 #ifndef __ASSEMBLY__ +#ifdef CONFIG_SMP +#ifdef CONFIG_PA20 +#define SMP_CACHE_BYTES (8 * L1_CACHE_BYTES) +#else +#define SMP_CACHE_BYTES (2 * L1_CACHE_BYTES) +#endif +#else #define SMP_CACHE_BYTES L1_CACHE_BYTES +#endif #define ARCH_DMA_MINALIGN L1_CACHE_BYTES