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[RFC,v3,7/7] drm/mediatek: enable hdmi output control bit

Message ID 1443627006-15319-8-git-send-email-p.zabel@pengutronix.de (mailing list archive)
State New, archived
Headers show

Commit Message

Philipp Zabel Sept. 30, 2015, 3:30 p.m. UTC 
From: Jie Qiu <jie.qiu@mediatek.com>

MT8173 HDMI hardware has a output control bit to enable/disable HDMI
output. Because of security reason, so this bit can ONLY be controlled
in ARM supervisor mode. Now the only way to enter ARM supervisor is the
ARM trusted firmware. So atf provides a API for HDMI driver to call to
setup this HDMI control bit to enable HDMI output in supervisor mode.

Signed-off-by: Jie Qiu <jie.qiu@mediatek.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 drivers/gpu/drm/mediatek/mtk_hdmi_hw.c   | 11 +++++++++++
 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h |  1 +
 2 files changed, 12 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
index 2d08b78..d7bc835 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
@@ -20,9 +20,16 @@ 
 #include <linux/io.h>
 #include <linux/compiler.h>
 #include <asm/cpu_ops.h>
+#include <linux/psci.h>
 #include <asm/smp_plat.h>
 #include <asm/system_misc.h>
 
+static int (*invoke_psci_fn)(u64, u64, u64, u64);
+typedef int (*psci_initcall_t)(const struct device_node *);
+
+asmlinkage int __invoke_psci_fn_hvc(u64, u64, u64, u64);
+asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64);
+
 #define MTK_HDMI_READ_BANK(bank) \
 static u32 mtk_hdmi_read_##bank(struct mtk_hdmi *hdmi, \
 				u32 offset) \
@@ -214,6 +221,10 @@  void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi,
 void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi,
 				   bool enable)
 {
+	invoke_psci_fn = __invoke_psci_fn_smc;
+	invoke_psci_fn(MTK_SIP_SET_AUTHORIZED_SECURE_REG,
+		       0x14000904, 0x80000000, 0);
+
 	if (enable) {
 		mtk_hdmi_mask_sys(hdmi, HDMI_SYS_CFG20, HDMI_PCLK_FREE_RUN,
 				  HDMI_PCLK_FREE_RUN);
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
index baf629b..41a9b1f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
@@ -351,4 +351,5 @@ 
 #define HDMI_PORD_INT_CLR  BIT(17)
 #define HDMI_FULL_INT_CLR  BIT(20)
 
+#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001
 #endif