drm/i915: Add GEN7_GPGPU_DISPATCHDIMX/Y/Z to the register whitelist
diff mbox

Message ID 1443766198-21640-1-git-send-email-jordan.l.justen@intel.com
State New
Headers show

Commit Message

Jordan Justen Oct. 2, 2015, 6:09 a.m. UTC
This is required to support glDispatchComputeIndirect for gen7.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
---
 drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +++++-
 drivers/gpu/drm/i915/i915_reg.h        | 4 ++++
 2 files changed, 9 insertions(+), 1 deletion(-)

Comments

Daniel Vetter Oct. 2, 2015, 8:06 a.m. UTC | #1
On Thu, Oct 01, 2015 at 11:09:58PM -0700, Jordan Justen wrote:
> This is required to support glDispatchComputeIndirect for gen7.
> 
> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

Do you have a link to the mesa patches? As soon as those are r-b'ed I'll
pull this in.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +++++-
>  drivers/gpu/drm/i915/i915_reg.h        | 4 ++++
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 09932ca..db58c8d 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -448,6 +448,9 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
>  	REG32(GEN7_3DPRIM_INSTANCE_COUNT),
>  	REG32(GEN7_3DPRIM_START_INSTANCE),
>  	REG32(GEN7_3DPRIM_BASE_VERTEX),
> +	REG32(GEN7_GPGPU_DISPATCHDIMX),
> +	REG32(GEN7_GPGPU_DISPATCHDIMY),
> +	REG32(GEN7_GPGPU_DISPATCHDIMZ),
>  	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
>  	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
>  	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
> @@ -1214,6 +1217,7 @@ int i915_cmd_parser_get_version(void)
>  	 *    MI_PREDICATE_SRC1 registers.
>  	 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
>  	 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
> +	 * 5. GPGPU dispatch compute indirect registers.
>  	 */
> -	return 4;
> +	return 5;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 56157eb..f2b6425 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -536,6 +536,10 @@
>  #define GEN7_3DPRIM_START_INSTANCE      0x243C
>  #define GEN7_3DPRIM_BASE_VERTEX         0x2440
>  
> +#define GEN7_GPGPU_DISPATCHDIMX         0x2500
> +#define GEN7_GPGPU_DISPATCHDIMY         0x2504
> +#define GEN7_GPGPU_DISPATCHDIMZ         0x2508
> +
>  #define OACONTROL 0x2360
>  
>  #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
> -- 
> 2.5.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Jordan Justen Oct. 2, 2015, 3:33 p.m. UTC | #2
On 2015-10-02 01:06:01, Daniel Vetter wrote:
> On Thu, Oct 01, 2015 at 11:09:58PM -0700, Jordan Justen wrote:
> > This is required to support glDispatchComputeIndirect for gen7.
> > 
> > Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
> > Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
> 
> Do you have a link to the mesa patches? As soon as those are r-b'ed I'll
> pull this in.

The patch that uses these registers in mesa is already upstream.

http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebbe6cdad7ab082d2b191fe6c7c0eaa6921d55de

-Jordan

> > ---
> >  drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +++++-
> >  drivers/gpu/drm/i915/i915_reg.h        | 4 ++++
> >  2 files changed, 9 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index 09932ca..db58c8d 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -448,6 +448,9 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
> >       REG32(GEN7_3DPRIM_INSTANCE_COUNT),
> >       REG32(GEN7_3DPRIM_START_INSTANCE),
> >       REG32(GEN7_3DPRIM_BASE_VERTEX),
> > +     REG32(GEN7_GPGPU_DISPATCHDIMX),
> > +     REG32(GEN7_GPGPU_DISPATCHDIMY),
> > +     REG32(GEN7_GPGPU_DISPATCHDIMZ),
> >       REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
> >       REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
> >       REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
> > @@ -1214,6 +1217,7 @@ int i915_cmd_parser_get_version(void)
> >        *    MI_PREDICATE_SRC1 registers.
> >        * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
> >        * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
> > +      * 5. GPGPU dispatch compute indirect registers.
> >        */
> > -     return 4;
> > +     return 5;
> >  }
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 56157eb..f2b6425 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -536,6 +536,10 @@
> >  #define GEN7_3DPRIM_START_INSTANCE      0x243C
> >  #define GEN7_3DPRIM_BASE_VERTEX         0x2440
> >  
> > +#define GEN7_GPGPU_DISPATCHDIMX         0x2500
> > +#define GEN7_GPGPU_DISPATCHDIMY         0x2504
> > +#define GEN7_GPGPU_DISPATCHDIMZ         0x2508
> > +
> >  #define OACONTROL 0x2360
> >  
> >  #define _GEN7_PIPEA_DE_LOAD_SL       0x70068
> > -- 
> > 2.5.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
Daniel Vetter Oct. 6, 2015, 8:40 a.m. UTC | #3
On Fri, Oct 02, 2015 at 08:33:45AM -0700, Jordan Justen wrote:
> On 2015-10-02 01:06:01, Daniel Vetter wrote:
> > On Thu, Oct 01, 2015 at 11:09:58PM -0700, Jordan Justen wrote:
> > > This is required to support glDispatchComputeIndirect for gen7.
> > > 
> > > Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
> > > Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
> > 
> > Do you have a link to the mesa patches? As soon as those are r-b'ed I'll
> > pull this in.
> 
> The patch that uses these registers in mesa is already upstream.
> 
> http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebbe6cdad7ab082d2b191fe6c7c0eaa6921d55de

This tends to royally piss of Dave, and last time around mesa was merged
before the kernel Dave just reverted everything and broke the mesa build.

Please never commit mesa patches before the kernel side has landed, ever.

I've pulled this one in here meanwhile to cover this up.
Thanks, Daniel

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 09932ca..db58c8d 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -448,6 +448,9 @@  static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
 	REG32(GEN7_3DPRIM_INSTANCE_COUNT),
 	REG32(GEN7_3DPRIM_START_INSTANCE),
 	REG32(GEN7_3DPRIM_BASE_VERTEX),
+	REG32(GEN7_GPGPU_DISPATCHDIMX),
+	REG32(GEN7_GPGPU_DISPATCHDIMY),
+	REG32(GEN7_GPGPU_DISPATCHDIMZ),
 	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
 	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
 	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
@@ -1214,6 +1217,7 @@  int i915_cmd_parser_get_version(void)
 	 *    MI_PREDICATE_SRC1 registers.
 	 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
 	 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
+	 * 5. GPGPU dispatch compute indirect registers.
 	 */
-	return 4;
+	return 5;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 56157eb..f2b6425 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -536,6 +536,10 @@ 
 #define GEN7_3DPRIM_START_INSTANCE      0x243C
 #define GEN7_3DPRIM_BASE_VERTEX         0x2440
 
+#define GEN7_GPGPU_DISPATCHDIMX         0x2500
+#define GEN7_GPGPU_DISPATCHDIMY         0x2504
+#define GEN7_GPGPU_DISPATCHDIMZ         0x2508
+
 #define OACONTROL 0x2360
 
 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068